Lines Matching refs:virtPtr
377 tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr;
378 tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t));
399 tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr;
400 tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t));
416 tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr;
417 tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t));
433 tdsaRoot = tdSharedMem->tdSharedCachedMem1.virtPtr;
434 tdsaPortContext = (tdsaPortContext_t *)((bitptr)tdSharedMem->tdSharedCachedMem1.virtPtr + sizeof(tdsaRoot_t));
450 IniAddr = initiatorResource->initiatorMem.tdCachedMem[0].virtPtr;
461 TgtAddr = targetResource->targetMem.tdMem[0].virtPtr;
2091 loResource->loLevelMem.mem[i].virtPtr = agNULL;
2210 loResource->loLevelMem.mem[i].virtPtr = agNULL;
2301 loResource->loLevelMem.mem[i].virtPtr = agNULL;
2393 loResource->loLevelMem.mem[i].virtPtr = agNULL;
2514 tdSharedMem->tdSharedCachedMem1.virtPtr = agNULL;