sallsdk/spc/sainit.c

1845   static spc_outboundQueueDescriptor_t outQueueCfg;       /* Outbound queue HW configuration structure */
1883   si_memset(&outQueueCfg,0,sizeof(spc_outboundQueueDescriptor_t));
2376       outQueueCfg.upperBaseAddress   = 0;
2377       outQueueCfg.lowerBaseAddress   = 0;
2378       outQueueCfg.piUpperBaseAddress = 0;
2379       outQueueCfg.piLowerBaseAddress = 0;
2380       /* skip outQueueCfg.CIPCIBar = 0; read access only */
2381       /* skip outQueueCfg.CIOffset = 0; read access only */
2382       outQueueCfg.elementSizeCount     = 0;
2383       outQueueCfg.interruptVecCntDelay = 0;
2386       mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar);
2429         outQueueCfg.upperBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrUpper;
2430         outQueueCfg.lowerBaseAddress = saRoot->outboundQueue[qIdx].memoryRegion.physAddrLower;
2433         outQueueCfg.piUpperBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrUpper;
2434         outQueueCfg.piLowerBaseAddress = memoryAllocated->region[MPI_CI_INDEX + 1].physAddrLower + qIdx * 4;
2435         outQueueCfg.elementSizeCount = config->outboundQueues[qIdx].numElements |
2445           outQueueCfg.elementSizeCount |= OB_PROPERTY_INT_ENABLE;
2449           outQueueCfg.interruptVecCntDelay = ((config->outboundQueues[qIdx].interruptVector    & INT_VEC_BITS  ) << SHIFT24);
2453           outQueueCfg.interruptVecCntDelay =  (config->outboundQueues[qIdx].interruptDelay     & INT_DELAY_BITS)             |
2470         mpiUpdateOBQueueCfgTable(agRoot, &outQueueCfg, MSGUCfgTblDWIdx, pcibar);
3533 /** \fn void mpiUpdateIBQueueCfgTable(agsaRoot_t *agRoot, spc_inboundQueueDescriptor_t *outQueueCfg,
3537  *  \param outQueueCfg      Pointer to inbuond configuration area
3574 /** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg,
3579  *  \param outQueueCfg      Pointer to outbuond configuration area
3588                               spc_outboundQueueDescriptor_t *outQueueCfg,
3595   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount);
3596   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress);
3597   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress);
3598   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress);
3599   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress);
3600   ossaHwRegWriteExt(agRoot, pcibar, (bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay);
3602   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x elementSizeCount     0x%x\n",(bit32)(QueueTableOffset + OB_PROPERITY_OFFSET), outQueueCfg->elementSizeCount));
3603   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x upperBaseAddress     0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_HI_OFFSET), outQueueCfg->upperBaseAddress));
3604   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x lowerBaseAddress     0x%x\n",(bit32)(QueueTableOffset + OB_BASE_ADDR_LO_OFFSET), outQueueCfg->lowerBaseAddress));
3605   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piUpperBaseAddress   0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_HI_OFFSET), outQueueCfg->piUpperBaseAddress));
3606   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x piLowerBaseAddress   0x%x\n",(bit32)(QueueTableOffset + OB_PI_BASE_ADDR_LO_OFFSET), outQueueCfg->piLowerBaseAddress));
3607   SA_DBG3(("mpiUpdateOBQueueCfgTable: Offset 0x%08x interruptVecCntDelay 0x%x\n",(bit32)(QueueTableOffset + OB_INTERRUPT_COALES_OFFSET), outQueueCfg->interruptVecCntDelay));
3614 /** \fn void mpiUpdateOBQueueCfgTable(agsaRoot_t *agRoot, spc_outboundQueueDescriptor_t *outQueueCfg,
3619  *  \param outQueueCfg      Pointer to outbuond configuration area