dev/pci/pci.c

766 			cfg->msix.msix_location = ptr;
767 			cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
768 			cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
771 			cfg->msix.msix_table_bar = PCIR_BAR(val &
773 			cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
775 			cfg->msix.msix_pba_bar = PCIR_BAR(val &
777 			cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
1380 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1383 	KASSERT(msix->msix_table_len > index, ("bogus index"));
1384 	offset = msix->msix_table_offset + index * 16;
1385 	bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1386 	bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1387 	bus_write_4(msix->msix_table_res, offset + 8, data);
1397 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1400 	KASSERT(msix->msix_msgnum > index, ("bogus index"));
1401 	offset = msix->msix_table_offset + index * 16 + 12;
1402 	val = bus_read_4(msix->msix_table_res, offset);
1405 		bus_write_4(msix->msix_table_res, offset, val);
1413 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1416 	KASSERT(msix->msix_table_len > index, ("bogus index"));
1417 	offset = msix->msix_table_offset + index * 16 + 12;
1418 	val = bus_read_4(msix->msix_table_res, offset);
1421 		bus_write_4(msix->msix_table_res, offset, val);
1429 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1432 	KASSERT(msix->msix_table_len > index, ("bogus index"));
1433 	offset = msix->msix_pba_offset + (index / 32) * 4;
1435 	return (bus_read_4(msix->msix_pba_res, offset) & bit);
1447 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1452 	if (msix->msix_alloc > 0) {
1454 		for (i = 0; i < msix->msix_msgnum; i++)
1458 		for (i = 0; i < msix->msix_table_len; i++) {
1459 			mte = &msix->msix_table[i];
1462 			mv = &msix->msix_vectors[mte->mte_vector - 1];
1467 	pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1468 	    msix->msix_ctrl, 2);
1494 	if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1502 	if (cfg->msix.msix_location == 0 || !pci_do_msix)
1507 	    cfg->msix.msix_table_bar);
1511 	cfg->msix.msix_table_res = rle->res;
1512 	if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1514 		    cfg->msix.msix_pba_bar);
1519 	cfg->msix.msix_pba_res = rle->res;
1524 		    *count, cfg->msix.msix_msgnum);
1525 	max = min(*count, cfg->msix.msix_msgnum);
1585 	for (i = 0; i < cfg->msix.msix_msgnum; i++)
1589 	cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1591 	cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1595 		cfg->msix.msix_vectors[i].mv_irq = rle->start;
1596 		cfg->msix.msix_table[i].mte_vector = i + 1;
1600 	cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1601 	pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1602 	    cfg->msix.msix_ctrl, 2);
1605 	cfg->msix.msix_alloc = actual;
1606 	cfg->msix.msix_table_len = actual;
1655 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1664 	if (count == 0 || count > msix->msix_msgnum)
1669 		if (vectors[i] > msix->msix_alloc)
1677 	used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1682 	for (i = 0; i < msix->msix_alloc - 1; i++)
1693 	for (i = 0; i < msix->msix_table_len; i++) {
1694 		if (msix->msix_table[i].mte_vector == 0)
1696 		if (msix->msix_table[i].mte_handlers > 0)
1705 	for (i = 0; i < msix->msix_table_len; i++) {
1706 		if (msix->msix_table[i].mte_vector == 0)
1715 	free(msix->msix_table, M_DEVBUF);
1716 	msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1719 		msix->msix_table[i].mte_vector = vectors[i];
1720 	msix->msix_table_len = count;
1723 	j = msix->msix_alloc - 1;
1729 			    msix->msix_vectors[j].mv_irq);
1734 		bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1736 		free(msix->msix_vectors, M_DEVBUF);
1737 		msix->msix_vectors = vec;
1738 		msix->msix_alloc = j + 1;
1746 		irq = msix->msix_vectors[vectors[i]].mv_irq;
1760 				    msix->msix_vectors[vectors[i]].mv_irq);
1772 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1777 	if (msix->msix_alloc == 0)
1781 	for (i = 0; i < msix->msix_table_len; i++) {
1782 		if (msix->msix_table[i].mte_vector == 0)
1784 		if (msix->msix_table[i].mte_handlers > 0)
1793 	msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1794 	pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1795 	    msix->msix_ctrl, 2);
1798 	for (i = 0; i < msix->msix_table_len; i++) {
1799 		if (msix->msix_table[i].mte_vector == 0)
1803 	free(msix->msix_table, M_DEVBUF);
1804 	msix->msix_table_len = 0;
1807 	for (i = 0; i < msix->msix_alloc; i++)
1809 		    msix->msix_vectors[i].mv_irq);
1810 	free(msix->msix_vectors, M_DEVBUF);
1811 	msix->msix_alloc = 0;
1825 	struct pcicfg_msix *msix = &dinfo->cfg.msix;
1827 	if (pci_do_msix && msix->msix_location != 0)
1828 		return (msix->msix_msgnum);
2019 	if (cfg->msix.msix_alloc > 0) {
2020 		for (i = 0; i < cfg->msix.msix_alloc; i++) {
2021 			mv = &cfg->msix.msix_vectors[i];
2029 				for (j = 0; j < cfg->msix.msix_table_len; j++) {
2030 					mte = &cfg->msix.msix_table[j];
2160 	if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2592 		if (cfg->msix.msix_location) {
2594 			    cfg->msix.msix_msgnum,
2595 			    (cfg->msix.msix_msgnum == 1) ? "" : "s");
2596 			if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2598 				    cfg->msix.msix_table_bar);
2601 				    cfg->msix.msix_table_bar,
2602 				    cfg->msix.msix_pba_bar);
3858 			KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3860 			KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3862 			mte = &dinfo->cfg.msix.msix_table[rid - 1];
3864 			mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3946 			KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3948 			KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3950 			mte = &dinfo->cfg.msix.msix_table[rid - 1];
4150 	if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
4597 		    cfg->msix.msix_alloc > 0))
4982 	if (dinfo->cfg.msix.msix_location != 0)