Lines Matching defs:new_config
34 * @new_config: tti configuration information
40 __hal_tti_config_check (xge_hal_tti_config_t *new_config)
42 if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) ||
43 (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) {
47 if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) ||
48 (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) {
52 if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) ||
53 (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) {
57 if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) ||
58 (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) {
62 if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) ||
63 (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) {
67 if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) ||
68 (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) {
72 if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) ||
73 (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) {
77 if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) ||
78 (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) {
82 if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) ||
83 (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) {
87 if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) ||
88 (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) {
97 * @new_config: rti configuration information
103 __hal_rti_config_check (xge_hal_rti_config_t *new_config)
105 if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) ||
106 (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) {
110 if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) ||
111 (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) {
115 if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) ||
116 (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) {
120 if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) ||
121 (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) {
125 if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) ||
126 (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) {
130 if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) ||
131 (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) {
135 if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) ||
136 (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) {
140 if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) ||
141 (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) {
145 if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) ||
146 (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) {
156 * @new_config: fifo queue configuration information
162 __hal_fifo_queue_check (xge_hal_fifo_config_t *new_config,
182 if (new_queue->max < new_config->reserve_threshold) {
216 * @new_config: ring queue configuration information
222 __hal_ring_queue_check (xge_hal_ring_queue_t *new_config)
225 if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
226 (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
233 new_config->max = new_config->initial;
235 if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) ||
236 (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) {
240 if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) &&
241 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) &&
242 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) {
250 if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) ||
251 (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) &&
252 new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE)
255 if ((new_config->backoff_interval_us <
257 (new_config->backoff_interval_us >
262 if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) ||
263 (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) {
267 if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) ||
268 (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) {
272 if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) ||
273 (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) {
277 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) ||
278 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) {
282 if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_PORT_EN) ||
283 (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) {
287 if ((new_config->intr_vector < XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR) ||
288 (new_config->intr_vector > XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR)) {
292 if (new_config->indicate_max_pkts <
294 new_config->indicate_max_pkts >
299 return __hal_rti_config_check(&new_config->rti);
304 * @new_config: mac configuration information
310 __hal_mac_config_check (xge_hal_mac_config_t *new_config)
312 if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) ||
313 (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) {
317 if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) ||
318 (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) {
322 if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) ||
323 (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) {
327 if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) ||
328 (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) {
332 if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) ||
333 (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) {
337 if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) ||
338 (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) {
342 if ((new_config->media < XGE_HAL_MIN_MEDIA) ||
343 (new_config->media > XGE_HAL_MAX_MEDIA)) {
347 if ((new_config->mc_pause_threshold_q0q3 <
349 (new_config->mc_pause_threshold_q0q3 >
354 if ((new_config->mc_pause_threshold_q4q7 <
356 (new_config->mc_pause_threshold_q4q7 >
366 * @new_config: fifo configuration information
372 __hal_fifo_config_check (xge_hal_fifo_config_t *new_config)
381 new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2;
383 if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) ||
384 (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS)) {
388 if ((new_config->reserve_threshold <
390 (new_config->reserve_threshold >
395 if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) ||
396 (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) {
403 if (!new_config->queue[i].configured)
406 if ((status = __hal_fifo_queue_check(new_config,
407 &new_config->queue[i])) != XGE_HAL_OK) {
411 total_fifo_length += new_config->queue[i].max;
423 * @new_config: Ring configuration information
429 __hal_ring_config_check (xge_hal_ring_config_t *new_config)
433 if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) ||
434 (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) {
441 if (!new_config->queue[i].configured)
444 if ((status = __hal_ring_queue_check(&new_config->queue[i]))
456 * @new_config: Device configuration information
467 __hal_device_config_check_common (xge_hal_device_config_t *new_config)
471 if ((new_config->mtu < XGE_HAL_MIN_MTU) ||
472 (new_config->mtu > XGE_HAL_MAX_MTU)) {
476 if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) ||
477 (new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) {
481 if (new_config->bimodal_interrupts &&
482 ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) ||
483 (new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) {
487 if (new_config->bimodal_interrupts &&
488 ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) ||
489 (new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) {
493 if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) ||
494 (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) {
498 if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) ||
499 (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) {
503 if (new_config->latency_timer &&
504 new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) {
505 if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) ||
506 (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) {
511 if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) {
512 if ((new_config->max_splits_trans <
514 (new_config->max_splits_trans >
519 if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT)
521 if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) ||
522 (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) {
527 if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) ||
528 (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) {
532 if (new_config->stats_refresh_time_sec !=
534 if ((new_config->stats_refresh_time_sec <
536 (new_config->stats_refresh_time_sec >
542 if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) &&
543 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) &&
544 (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) {
548 if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) ||
549 (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) {
553 if ((new_config->sched_timer_one_shot !=
555 (new_config->sched_timer_one_shot !=
569 if (new_config->sched_timer_us &&
570 new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) {
571 if ((new_config->rxufca_intr_thres <
573 (new_config->rxufca_intr_thres >
578 if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) ||
579 (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) {
583 if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) ||
584 (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) ||
585 (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) {
589 if ((new_config->rxufca_lbolt_period <
591 (new_config->rxufca_lbolt_period >
597 if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) ||
598 (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) {
602 if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) ||
603 (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) {
607 if (new_config->link_valid_cnt > new_config->link_retry_cnt)
610 if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) {
611 if ((new_config->link_stability_period <
613 (new_config->link_stability_period >
619 if (new_config->device_poll_millis !=
621 if ((new_config->device_poll_millis <
623 (new_config->device_poll_millis >
629 if ((new_config->rts_port_en < XGE_HAL_MIN_RING_RTS_PORT_EN) ||
630 (new_config->rts_port_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) {
634 if ((new_config->rts_qos_en < XGE_HAL_RTS_QOS_DISABLE) ||
635 (new_config->rts_qos_en > XGE_HAL_RTS_QOS_ENABLE)) {
640 if (new_config->lro_sg_size !=
642 if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) ||
643 (new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) {
648 if (new_config->lro_frm_len !=
650 if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) ||
651 (new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) {
657 if ((status = __hal_ring_config_check(&new_config->ring))
662 if ((status = __hal_mac_config_check(&new_config->mac)) !=
667 if ((status = __hal_fifo_config_check(&new_config->fifo)) !=
677 * @new_config: Device configuration.
687 __hal_device_config_check_xena (xge_hal_device_config_t *new_config)
689 if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) &&
690 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) &&
691 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) &&
692 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) &&
693 (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) &&
694 (new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) {
703 * @new_config: Device configuration.
713 __hal_device_config_check_herc (xge_hal_device_config_t *new_config)
721 * @new_config: Driver configuration information
727 __hal_driver_config_check (xge_hal_driver_config_t *new_config)
729 if ((new_config->queue_size_initial <
731 (new_config->queue_size_initial >
736 if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) ||
737 (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) {
742 if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) ||
743 (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) {
746 if ((new_config->tracebuf_timestamp_en < XGE_HAL_MIN_TIMESTAMP_EN) ||
747 (new_config->tracebuf_timestamp_en > XGE_HAL_MAX_TIMESTAMP_EN)) {