dev/nge/if_nge.c

247 		CSR_READ_4(sc, reg) | (x))
251 		CSR_READ_4(sc, reg) & ~(x))
254 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
257 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
265 		CSR_READ_4(sc, NGE_CSR);
349 		if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
389 	val = CSR_READ_4(sc, NGE_MEAR);
429 			reg = CSR_READ_4(sc, NGE_TBI_BMSR);
455 		return (CSR_READ_4(sc, reg));
589 		reg = CSR_READ_4(sc, NGE_CFG);
604 		reg = CSR_READ_4(sc, NGE_CSR);
611 			status = CSR_READ_4(sc, NGE_ISR);
642 		reg = CSR_READ_4(sc, NGE_CSR);
646 			if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0)
658 		    CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
673 	rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL);
757 		if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
783 	v = CSR_READ_4(sc, NGE_CFG);
928 	if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) {
932 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1709 	    CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF;
1711 	    CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF;
1713 	    CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF;
1715 	    CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF;
1717 	    CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF;
1719 	    CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF;
1721 	    CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF;
1723 	    CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF;
1725 	    CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF;
1727 	    CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF;
1729 	    CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF;
1785 		status = CSR_READ_4(sc, NGE_ISR);
1819 	status = CSR_READ_4(sc, NGE_ISR);
1835 		    CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT);
1855 		status = CSR_READ_4(sc, NGE_ISR);
1867 		    CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
2194 	reg = CSR_READ_4(sc, NGE_MIBCTL);
2436 	reg = CSR_READ_4(sc, NGE_CSR);
2443 			if ((CSR_READ_4(sc, NGE_CSR) &
2564 		reg = CSR_READ_4(sc, NGE_CLKRUN);