Lines Matching defs:WR4
221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
500 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
516 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
520 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
537 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
2183 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2360 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2363 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2449 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2460 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2463 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2466 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2495 WR4(mh, MACREG_REG_INT_CODE, 0);
2513 WR4(mh, MACREG_REG_INT_CODE, 0);
2526 WR4(mh, 0x00006014, 0x33);
2527 WR4(mh, 0x00006018, 0xa3a2632);
2528 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2578 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2579 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2580 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2581 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2611 WR4(mh, MACREG_REG_INT_CODE, 0);
2673 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2676 WR4(mh, MACREG_REG_INT_CODE, 0x00);