dev/msk/if_mskreg.h

507 #define B3_RI_WTO_R1	0x0190	/*  8 bit WR Timeout Queue R1 (TO0) */
508 #define B3_RI_WTO_XA1	0x0191	/*  8 bit WR Timeout Queue XA1 (TO1) */
509 #define B3_RI_WTO_XS1	0x0192	/*  8 bit WR Timeout Queue XS1 (TO2) */
510 #define B3_RI_RTO_R1	0x0193	/*  8 bit RD Timeout Queue R1 (TO3) */
511 #define B3_RI_RTO_XA1	0x0194	/*  8 bit RD Timeout Queue XA1 (TO4) */
512 #define B3_RI_RTO_XS1	0x0195	/*  8 bit RD Timeout Queue XS1 (TO5) */
513 #define B3_RI_WTO_R2	0x0196	/*  8 bit WR Timeout Queue R2 (TO6) */
514 #define B3_RI_WTO_XA2	0x0197	/*  8 bit WR Timeout Queue XA2 (TO7) */
515 #define B3_RI_WTO_XS2	0x0198	/*  8 bit WR Timeout Queue XS2 (TO8) */
516 #define B3_RI_RTO_R2	0x0199	/*  8 bit RD Timeout Queue R2 (TO9) */
517 #define B3_RI_RTO_XA2	0x019a	/*  8 bit RD Timeout Queue XA2 (TO10)*/
518 #define B3_RI_RTO_XS2	0x019b	/*  8 bit RD Timeout Queue XS2 (TO11)*/
551 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */
554 /* Queue Register Offsets, use Q_ADDR() to access */
579 #define Q_ADDR(Queue, Offs)	(B8_Q_REGS + (Queue) + (Offs))
581 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */
597 #define Y2_PREF_Q_ADDR(Queue, Offs)	(Y2_B8_PREF_REGS + (Queue) + (Offs))
870 #define Y2_IS_PAR_RX2	BIT_10	/* Parity Error Rx Queue 2 */
876 #define Y2_IS_PAR_RX1	BIT_2	/* Parity Error Rx Queue 1 */
1105 #define BMU_STOP		BIT_9	/* Stop  Rx/Tx Queue */
1106 #define BMU_START		BIT_8	/* Start Rx/Tx Queue */
1139 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1146 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
1199 #define Q_R1		0x0000	/* Receive Queue 1 */
1200 #define Q_R2		0x0080	/* Receive Queue 2 */
1201 #define Q_XS1		0x0200	/* Synchronous Transmit Queue 1 */
1202 #define Q_XA1		0x0280	/* Asynchronous Transmit Queue 1 */
1203 #define Q_XS2		0x0300	/* Synchronous Transmit Queue 2 */
1204 #define Q_XA2		0x0380	/* Asynchronous Transmit Queue 2 */
1206 #define Q_ASF_R1	0x100	/* ASF Rx Queue 1 */
1207 #define Q_ASF_R2	0x180	/* ASF Rx Queue 2 */
1208 #define Q_ASF_T1	0x140	/* ASF Tx Queue 1 */
1209 #define Q_ASF_T2	0x1c0	/* ASF Tx Queue 2 */
1211 #define RB_ADDR(Queue, Offs)	(B16_RAM_REGS + (Queue) + (Offs))
1213 /* Minimum RAM Buffer Rx Queue Size */
1215 /* Minimum RAM Buffer Tx Queue Size */
2581 	uint32_t		msk_txq;	/* Tx. Async Queue offset */
2582 	uint32_t		msk_txsq;	/* Tx. Syn Queue offset */