dev/ixl/i40e_adminq.c

61 		hw->aq.asq.tail = I40E_VF_ATQT1;
62 		hw->aq.asq.head = I40E_VF_ATQH1;
63 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
64 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
65 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
72 		hw->aq.asq.tail = I40E_PF_ATQT;
73 		hw->aq.asq.head = I40E_PF_ATQH;
74 		hw->aq.asq.len  = I40E_PF_ATQLEN;
75 		hw->aq.asq.bal  = I40E_PF_ATQBAL;
76 		hw->aq.asq.bah  = I40E_PF_ATQBAH;
93 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
101 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
105 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
138 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
231 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
235 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
239 		bi = &hw->aq.asq.r.asq_bi[i];
254 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
255 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
289 		if (hw->aq.asq.r.asq_bi[i].pa)
290 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
293 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
296 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
299 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
314 	wr32(hw, hw->aq.asq.head, 0);
315 	wr32(hw, hw->aq.asq.tail, 0);
318 	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
320 	wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
321 	wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
324 	reg = rd32(hw, hw->aq.asq.bal);
325 	if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
380 	if (hw->aq.asq.count > 0) {
393 	hw->aq.asq.next_to_use = 0;
394 	hw->aq.asq.next_to_clean = 0;
395 	hw->aq.asq.count = hw->aq.num_asq_entries;
491 	if (hw->aq.asq.count == 0)
495 	wr32(hw, hw->aq.asq.head, 0);
496 	wr32(hw, hw->aq.asq.tail, 0);
497 	wr32(hw, hw->aq.asq.len, 0);
498 	wr32(hw, hw->aq.asq.bal, 0);
499 	wr32(hw, hw->aq.asq.bah, 0);
504 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
680 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
682 	u16 ntc = asq->next_to_clean;
686 	desc = I40E_ADMINQ_DESC(*asq, ntc);
687 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
688 	while (rd32(hw, hw->aq.asq.head) != ntc) {
691 			   rd32(hw, hw->aq.asq.head));
703 		if (ntc == asq->count)
705 		desc = I40E_ADMINQ_DESC(*asq, ntc);
706 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
709 	asq->next_to_clean = ntc;
711 	return I40E_DESC_UNUSED(asq);
726 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
755 	val = rd32(hw, hw->aq.asq.head);
763 	if (hw->aq.asq.count == 0) {
776 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
838 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
846 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
865 	(hw->aq.asq.next_to_use)++;
866 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
867 		hw->aq.asq.next_to_use = 0;
869 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
1058 	hw->aq.asq.next_to_use = 0;
1059 	hw->aq.asq.next_to_clean = 0;