dev/iwi/if_iwi.c

337 		error = iwi_alloc_tx_ring(sc, &sc->txq[i], IWI_TX_RING_COUNT,
469 	iwi_free_tx_ring(sc, &sc->txq[0]);
470 	iwi_free_tx_ring(sc, &sc->txq[1]);
471 	iwi_free_tx_ring(sc, &sc->txq[2]);
472 	iwi_free_tx_ring(sc, &sc->txq[3]);
1595 iwi_tx_intr(struct iwi_softc *sc, struct iwi_tx_ring *txq)
1601 	hw = CSR_READ_4(sc, txq->csr_ridx);
1603 	for (; txq->next != hw;) {
1604 		data = &txq->data[txq->next];
1606 		bus_dmamap_sync(txq->data_dmat, data->map,
1608 		bus_dmamap_unload(txq->data_dmat, data->map);
1616 		DPRINTFN(15, ("tx done idx=%u\n", txq->next));
1620 		txq->queued--;
1621 		txq->next = (txq->next + 1) % IWI_TX_RING_COUNT;
1696 		iwi_tx_intr(sc, &sc->txq[0]);
1699 		iwi_tx_intr(sc, &sc->txq[1]);
1702 		iwi_tx_intr(sc, &sc->txq[2]);
1705 		iwi_tx_intr(sc, &sc->txq[3]);
1781 	struct iwi_tx_ring *txq = &sc->txq[ac];
1863 	data = &txq->data[txq->cur];
1864 	desc = &txq->desc[txq->cur];
1870 	error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1888 		error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map,
1922 	bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1923 	bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1925 	DPRINTFN(5, ("sending data frame txq=%u idx=%u len=%u nseg=%u\n",
1926 	    ac, txq->cur, le16toh(desc->len), nsegs));
1928 	txq->queued++;
1929 	txq->cur = (txq->cur + 1) % IWI_TX_RING_COUNT;
1930 	CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
1963 		if (sc->txq[ac].queued > IWI_TX_RING_COUNT - 8) {
3112 	CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].physaddr);
3113 	CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq[0].count);
3114 	CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur);
3116 	CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].physaddr);
3117 	CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq[1].count);
3118 	CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur);
3120 	CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].physaddr);
3121 	CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq[2].count);
3122 	CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur);
3124 	CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].physaddr);
3125 	CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq[3].count);
3126 	CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur);
3198 	iwi_reset_tx_ring(sc, &sc->txq[0]);
3199 	iwi_reset_tx_ring(sc, &sc->txq[1]);
3200 	iwi_reset_tx_ring(sc, &sc->txq[2]);
3201 	iwi_reset_tx_ring(sc, &sc->txq[3]);