dev/ieee488/upd7210.c

82 upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val)
145 	upd7210_wr(u, AUXMR, AUXMR_TCA);
162 	upd7210_wr(u, AUXMR, AUXMR_GTS);
207 				upd7210_wr(u, IMR1, 0);
236 	upd7210_wr(u, AUXMR, AUXMR_CRST); /* chip reset */
238 	upd7210_wr(u, AUXMR, C_ICR | 8); /* 8 MHz clock */
240 	upd7210_wr(u, ADR, 0x60); /* ADR0: disable listener and talker 0 */
241 	upd7210_wr(u, ADR, 0xe0); /* ADR1: disable listener and talker 1 */
242 	upd7210_wr(u, ADMR, 0x70); /* listen-only (lon) */
243 	upd7210_wr(u, AUXMR, AUXMR_PON); /* immediate execute power-on (pon) */
256 		upd7210_wr(u, IMR1, 0x01); /* data in interrupt enable */
275 	upd7210_wr(u, AUXMR, AUXMR_CRST);
277 	upd7210_wr(u, IMR1, 0x00);
278 	upd7210_wr(u, IMR2, 0x00);
323 			upd7210_wr(u, IMR1, 0x01);