dev/firewire/fwohci.c

97 	"No stat","Undef","long","miss Ack err",
318 	uint32_t fun, stat;
342 	stat = OREAD(sc, FWOHCI_INTSTAT);
343 	if ((stat & OHCI_INT_REG_FAIL) != 0 ||
1080 	u_int stat, status;
1121 		stat = status & FWOHCIEV_MASK;
1122 		switch(stat){
1130 			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1135 			device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1150 							stat, fwohcicode[stat]);
1170 				} else if (stat != FWOHCIEV_ACKPEND) {
1171 					if (stat != FWOHCIEV_ACKCOMPL)
1532 	uint32_t stat;
1586 	stat = OREAD(sc, OHCI_ITCTL(dmach));
1587 	if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1588 		printf("stat 0x%x\n", stat);
1590 	if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1605 		printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1610 	if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1636 	} else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1638 			"IT DMA underrun (0x%08x)\n", stat);
1651 	uint32_t stat;
1718 	stat = OREAD(sc, OHCI_IRCTL(dmach));
1719 	if (stat & OHCI_CNTL_DMA_ACTIVE)
1721 	if (stat & OHCI_CNTL_DMA_RUN) {
1723 		device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1727 		printf("start IR DMA 0x%x\n", stat);
1811 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
1813 	if(stat & OREAD(sc, FWOHCI_INTMASK))
1815 			stat & OHCI_INT_EN ? "DMA_EN ":"",
1816 			stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1817 			stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1818 			stat & OHCI_INT_ERR ? "INT_ERR ":"",
1819 			stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1820 			stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1821 			stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1822 			stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1823 			stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1824 			stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1825 			stat & OHCI_INT_PHY_SID ? "SID ":"",
1826 			stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1827 			stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1828 			stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1829 			stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1830 			stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1831 			stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1832 			stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1833 			stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1834 			stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1835 			stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1836 			stat, OREAD(sc, FWOHCI_INTMASK)
1841 fwohci_intr_core(struct fwohci_softc *sc, uint32_t stat, int count)
1847 	if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
1864 	if (stat & OHCI_INT_PHY_SID) {
1916 	if ((stat & ~(OHCI_INT_PHY_BUS_R | OHCI_INT_PHY_SID)) && (!kdb_active))
1921 fwohci_intr_dma(struct fwohci_softc *sc, uint32_t stat, int count)
1927 	if (stat & OHCI_INT_DMA_IR) {
1943 	if (stat & OHCI_INT_DMA_IT) {
1951 	if (stat & OHCI_INT_DMA_PRRS) {
1958 	if (stat & OHCI_INT_DMA_PRRQ) {
1965 	if (stat & OHCI_INT_CYC_LOST) {
1978 	if (stat & OHCI_INT_DMA_ATRQ) {
1981 	if (stat & OHCI_INT_DMA_ATRS) {
1984 	if (stat & OHCI_INT_PW_ERR) {
1987 	if (stat & OHCI_INT_ERR) {
1990 	if (stat & OHCI_INT_PHY_INT) {
2056 	uint32_t stat;
2059 	stat = atomic_readandclear_int(&sc->intstat);
2060 	if (stat)
2061 		fwohci_intr_dma(sc, stat, -1);
2070 	uint32_t stat, irstat, itstat;
2073 	stat = OREAD(sc, FWOHCI_INTSTAT);
2074 	if (stat == 0xffffffff) {
2080 	if (stat)
2081 		OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
2083 	stat &= sc->intmask;
2084 	if (stat == 0)
2087 	atomic_set_int(&sc->intstat, stat);
2088 	if (stat & OHCI_INT_DMA_IR) {
2093 	if (stat & OHCI_INT_DMA_IT) {
2099 	fwohci_intr_core(sc, stat, -1);
2147 	uint32_t stat, count;
2159 		stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2165 		if (stat == 0)
2168 		switch (stat & FWOHCIEV_MASK){
2177 					stat, fwohcicode[stat & 0x1f]);
2195 	uint32_t stat;
2210 		stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2212 		if (stat == 0)
2229 		switch (stat & FWOHCIEV_MASK) {
2237 					stat, fwohcicode[stat & 0x1f]);
2256 	uint32_t off, cntl, stat, cmd, match;
2271 	cntl = stat = OREAD(sc, off);
2280 	stat &= 0xffff ;
2281 	if (stat) {
2284 			stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2285 			stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2286 			stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2287 			stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2288 			stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2289 			stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2290 			fwohcicode[stat & 0x1f],
2291 			stat & 0x1f
2380 	fwohcireg_t stat;
2405 		stat = res >> OHCI_STATUS_SHIFT;
2420 				stat,
2422 		if(stat & 0xff00){
2424 				stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2425 				stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2426 				stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2427 				stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2428 				stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2429 				stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2430 				fwohcicode[stat & 0x1f],
2431 				stat & 0x1f
2751 	uint32_t stat, off, status, event;
2888 			stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
2890 			printf("plen: %d, stat %x\n",
2891 			    plen ,stat);
2893 			spd = (stat >> 21) & 0x3;
2894 			event = (stat >> 16) & 0x1f;
2924 				    " tcode=0x%x, stat=0x%08x\n",
2928 				    fp->mode.common.tcode, stat);