Lines Matching refs:u_short
237 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
239 #define WINDOW_SELECT (u_short) (0x1<<11)
240 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
246 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
248 #define RX_ENABLE (u_short) (0x4<<11)
249 #define RX_RESET (u_short) (0x5<<11)
250 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
251 #define TX_ENABLE (u_short) (0x9<<11)
252 #define TX_DISABLE (u_short) (0xa<<11)
253 #define TX_RESET (u_short) (0xb<<11)
254 #define REQ_INTR (u_short) (0xc<<11)
259 #define ACK_INTR (u_short) (0x6800)
260 # define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
261 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
262 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
263 # define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
264 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
265 # define C_RX_EARLY (u_short) (ACK_INTR|0x20)
266 # define C_INT_RQD (u_short) (ACK_INTR|0x40)
267 # define C_UPD_STATS (u_short) (ACK_INTR|0x80)
268 #define SET_INTR_MASK (u_short) (0xe<<11)
269 #define SET_RD_0_MASK (u_short) (0xf<<11)
270 #define SET_RX_FILTER (u_short) (0x10<<11)
271 # define FIL_INDIVIDUAL (u_short) (0x1)
272 # define FIL_MULTICAST (u_short) (0x02)
273 # define FIL_BRDCST (u_short) (0x04)
274 # define FIL_PROMISC (u_short) (0x08)
275 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
276 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
277 #define SET_TX_START_THRESH (u_short) (0x13<<11)
278 #define STATS_ENABLE (u_short) (0x15<<11)
279 #define STATS_DISABLE (u_short) (0x16<<11)
280 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
281 #define TX_PLL_ENABLE (u_short) (0x18<<11)
282 #define TX_PLL_DISABLE (u_short) (0x19<<11)
283 #define POWER_UP (u_short) (0x1b<<11)
284 #define POWER_DOWN (u_short) (0x1b<<11)
285 #define POWER_AUTO (u_short) (0x1b<<11)
305 #define S_INTR_LATCH (u_short) (0x1)
306 #define S_CARD_FAILURE (u_short) (0x2)
307 #define S_TX_COMPLETE (u_short) (0x4)
308 #define S_TX_AVAIL (u_short) (0x8)
309 #define S_RX_COMPLETE (u_short) (0x10)
310 #define S_RX_EARLY (u_short) (0x20)
311 #define S_INT_RQD (u_short) (0x40)
312 #define S_UPD_STATS (u_short) (0x80)
313 #define S_MASK (u_short) 0xFF /* mask of S_* */
316 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
336 ((u_short)(irq)<<12)) ) /* set IRQ i */
355 #define ERR_RX_INCOMPLETE (u_short) (0x1<<15)
356 #define ERR_RX (u_short) (0x1<<14)
357 #define ERR_RX_OVERRUN (u_short) (0x8<<11)
358 #define ERR_RX_RUN_PKT (u_short) (0xb<<11)
359 #define ERR_RX_ALIGN (u_short) (0xc<<11)
360 #define ERR_RX_CRC (u_short) (0xd<<11)
361 #define ERR_RX_OVERSIZE (u_short) (0x9<<11)
362 #define ERR_RX_DRIBBLE (u_short) (0x2<<11)
434 #define RX_BYTES_MASK (u_short) (0x07ff)