dev/ep/if_ep.c

401 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
416 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
417 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
426 	CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
428 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
429 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
432 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
435 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
442 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
443 	CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);
444 	CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
458 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
459 	CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);
498 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
518 		CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
526 		CSR_WRITE_2(sc, EP_COMMAND,
578 			CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
612 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);	/* disable all Ints */
619 		CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));
672 					CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
686 					CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
692 						CSR_WRITE_2(sc, EP_COMMAND,
705 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);	/* ACK int Latch */
711 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
824 		CSR_WRITE_2(sc, EP_COMMAND,
828 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
846 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
850 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
860 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
870 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
886 			CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);
1002 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);
1003 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
1006 	CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);
1007 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
1010 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
1012 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
1015 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);
1016 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);
1017 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);
1018 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);