Lines Matching refs:gb_addr_config
1565 u32 gb_addr_config = 0;
1588 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1605 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1623 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1657 gb_addr_config &= ~ROW_SIZE_MASK;
1661 gb_addr_config |= ROW_SIZE(0);
1664 gb_addr_config |= ROW_SIZE(1);
1667 gb_addr_config |= ROW_SIZE(2);
1671 /* setup tiling info dword. gb_addr_config is not adequate since it does
1708 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1710 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1712 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1713 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1714 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1715 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1716 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1717 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);