Lines Matching refs:PACKET3
1803 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1806 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1815 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1833 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1836 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1841 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1847 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1854 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1869 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1872 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1950 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1959 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1974 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1980 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1984 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1987 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2999 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
3082 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3097 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3105 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3113 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));