Lines Matching refs:link_width_cntl
1224 u32 link_width_cntl, lanes, speed_cntl, tmp;
1252 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1253 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1254 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1255 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1256 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1257 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1258 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1260 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1262 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1264 link_width_cntl |= LC_UPCONFIGURE_DIS;
1265 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1298 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1301 link_width_cntl |= LC_UPCONFIGURE_DIS;
1303 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1304 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);