Lines Matching refs:dev_priv
67 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
69 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
73 if (dev_priv->flags & RADEON_IS_AGP) {
74 val = DRM_READ32(dev_priv->ring_rptr, off);
77 dev_priv->ring_rptr->handle) +
84 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
86 if (dev_priv->writeback_works)
87 return radeon_read_ring_rptr(dev_priv, 0);
89 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
96 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
98 if (dev_priv->flags & RADEON_IS_AGP)
99 DRM_WRITE32(dev_priv->ring_rptr, off, val);
101 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
105 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
107 radeon_write_ring_rptr(dev_priv, 0, val);
110 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
112 if (dev_priv->writeback_works) {
113 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
114 return radeon_read_ring_rptr(dev_priv,
117 return radeon_read_ring_rptr(dev_priv,
120 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
127 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
136 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
145 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
154 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
163 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
165 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
166 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
167 return RS690_READ_MCIND(dev_priv, addr);
168 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
169 return RS600_READ_MCIND(dev_priv, addr);
171 return RS480_READ_MCIND(dev_priv, addr);
174 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
177 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
182 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
183 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
185 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
186 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
187 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
188 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
189 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
194 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
196 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
202 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
203 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
205 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
207 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
213 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
216 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
219 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
222 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
224 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
225 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
227 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
229 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
235 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
242 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
244 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
246 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
249 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
250 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
253 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
256 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
259 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
260 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
265 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
270 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
274 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
279 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
280 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
282 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
291 drm_radeon_private_t *dev_priv = dev->dev_private;
297 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
304 static void radeon_status(drm_radeon_private_t * dev_priv)
330 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
335 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
337 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
342 for (i = 0; i < dev_priv->usec_timeout; i++) {
356 radeon_status(dev_priv);
361 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
365 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
367 for (i = 0; i < dev_priv->usec_timeout; i++) {
380 radeon_status(dev_priv);
385 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
389 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
391 ret = radeon_do_wait_for_fifo(dev_priv, 64);
395 for (i = 0; i < dev_priv->usec_timeout; i++) {
398 radeon_do_pixcache_flush(dev_priv);
409 radeon_status(dev_priv);
416 drm_radeon_private_t *dev_priv = dev->dev_private;
419 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
422 dev_priv->num_z_pipes = 2;
424 dev_priv->num_z_pipes = 1;
426 dev_priv->num_z_pipes = 1;
429 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
431 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
435 dev_priv->num_gb_pipes = 1;
438 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
440 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
442 dev_priv->num_gb_pipes = 2;
445 dev_priv->num_gb_pipes = 1;
448 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
452 switch (dev_priv->num_gb_pipes) {
460 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
462 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
465 radeon_do_wait_for_idle(dev_priv);
479 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
486 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
487 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
488 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
493 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
495 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
499 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
500 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
507 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
508 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
509 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
512 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
513 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
516 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
519 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
520 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
521 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
531 dev_priv->me_fw = firmware_get(fw_name);
532 if (dev_priv->me_fw == NULL) {
536 } else if (dev_priv->me_fw->datasize % 8) {
539 dev_priv->me_fw->datasize, fw_name);
541 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
542 dev_priv->me_fw = NULL;
547 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
552 radeon_do_wait_for_idle(dev_priv);
554 if (dev_priv->me_fw) {
555 size = dev_priv->me_fw->datasize / 4;
556 fw_data = (const __be32 *)dev_priv->me_fw->data;
571 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
584 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
598 return radeon_do_wait_for_idle(dev_priv);
603 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
608 radeon_do_wait_for_idle(dev_priv);
610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
612 dev_priv->cp_running = 1;
617 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
639 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
646 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
653 SET_RING_HEAD(dev_priv, cur_read_ptr);
654 dev_priv->ring.tail = cur_read_ptr;
661 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
667 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
673 radeon_do_wait_for_idle(dev_priv);
678 dev_priv->cp_running = 0;
685 drm_radeon_private_t *dev_priv = dev->dev_private;
689 radeon_do_pixcache_flush(dev_priv);
691 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
726 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
737 radeon_do_cp_reset(dev_priv);
740 dev_priv->cp_running = 0;
749 drm_radeon_private_t *dev_priv,
760 if (!dev_priv->new_memmap)
761 radeon_write_fb_location(dev_priv,
762 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
763 | (dev_priv->fb_location >> 16));
766 if (dev_priv->flags & RADEON_IS_AGP) {
767 radeon_write_agp_base(dev_priv, dev->agp->base);
769 radeon_write_agp_location(dev_priv,
770 (((dev_priv->gart_vm_start - 1 +
771 dev_priv->gart_size) & 0xffff0000) |
772 (dev_priv->gart_vm_start >> 16)));
774 ring_start = (dev_priv->cp_ring->offset
776 + dev_priv->gart_vm_start);
779 ring_start = (dev_priv->cp_ring->offset
781 + dev_priv->gart_vm_start);
791 SET_RING_HEAD(dev_priv, cur_read_ptr);
792 dev_priv->ring.tail = cur_read_ptr;
795 if (dev_priv->flags & RADEON_IS_AGP) {
797 dev_priv->ring_rptr->offset
798 - dev->agp->base + dev_priv->gart_vm_start);
803 dev_priv->ring_rptr->offset
805 + dev_priv->gart_vm_start);
812 (dev_priv->ring.fetch_size_l2ow << 18) |
813 (dev_priv->ring.rptr_update_l2qw << 8) |
814 dev_priv->ring.size_l2qw);
817 (dev_priv->ring.fetch_size_l2ow << 18) |
818 (dev_priv->ring.rptr_update_l2qw << 8) |
819 dev_priv->ring.size_l2qw);
835 radeon_enable_bm(dev_priv);
837 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
840 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
843 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
854 radeon_do_wait_for_idle(dev_priv);
865 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
870 dev_priv->writeback_works = 0;
875 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
879 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
882 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
888 if (tmp < dev_priv->usec_timeout) {
889 dev_priv->writeback_works = 1;
892 dev_priv->writeback_works = 0;
896 dev_priv->writeback_works = 0;
900 if (!dev_priv->writeback_works) {
909 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
915 dev_priv->gart_vm_start,
916 (long)dev_priv->gart_info.bus_addr,
917 dev_priv->gart_size);
919 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
920 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
930 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
936 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
937 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
940 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
944 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
946 dev_priv->gart_size = 32*1024*1024;
947 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
948 0xffff0000) | (dev_priv->gart_vm_start >> 16));
950 radeon_write_agp_location(dev_priv, temp);
952 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
980 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
987 dev_priv->gart_vm_start,
988 (long)dev_priv->gart_info.bus_addr,
989 dev_priv->gart_size);
1012 dev_priv->gart_info.bus_addr);
1014 dev_priv->gart_vm_start);
1016 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1021 dev_priv->gart_vm_start);
1023 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1026 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1029 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1033 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1037 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1041 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1045 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1049 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1055 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1057 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1061 dev_priv->gart_vm_start,
1062 (long)dev_priv->gart_info.bus_addr,
1063 dev_priv->gart_size);
1065 dev_priv->gart_vm_start);
1067 dev_priv->gart_info.bus_addr);
1069 dev_priv->gart_vm_start);
1071 dev_priv->gart_vm_start +
1072 dev_priv->gart_size - 1);
1074 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1085 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1089 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1090 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1091 (dev_priv->flags & RADEON_IS_IGPGART)) {
1092 radeon_set_igpgart(dev_priv, on);
1096 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1097 rs600_set_igpgart(dev_priv, on);
1101 if (dev_priv->flags & RADEON_IS_PCIE) {
1102 radeon_set_pciegart(dev_priv, on);
1114 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1118 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1119 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1120 + dev_priv->gart_size - 1);
1124 radeon_write_agp_location(dev_priv, 0xffffffc0);
1132 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1134 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1139 if (!dev_priv->virt_surfaces[i].file_priv ||
1140 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1145 vp = &dev_priv->virt_surfaces[i];
1148 struct radeon_surface *sp = &dev_priv->surfaces[i];
1175 drm_radeon_private_t *dev_priv = dev->dev_private;
1181 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1187 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1189 dev_priv->flags &= ~RADEON_IS_AGP;
1190 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1193 dev_priv->flags |= RADEON_IS_AGP;
1196 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1202 dev_priv->usec_timeout = init->usec_timeout;
1203 if (dev_priv->usec_timeout < 1 ||
1204 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1212 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1216 dev_priv->microcode_version = UCODE_R200;
1219 dev_priv->microcode_version = UCODE_R300;
1222 dev_priv->microcode_version = UCODE_R100;
1225 dev_priv->do_boxes = 0;
1226 dev_priv->cp_mode = init->cp_mode;
1241 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1245 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1248 dev_priv->front_offset = init->front_offset;
1249 dev_priv->front_pitch = init->front_pitch;
1250 dev_priv->back_offset = init->back_offset;
1251 dev_priv->back_pitch = init->back_pitch;
1255 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1259 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1262 dev_priv->depth_offset = init->depth_offset;
1263 dev_priv->depth_pitch = init->depth_pitch;
1270 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1271 (dev_priv->color_fmt << 10) |
1272 (dev_priv->microcode_version ==
1275 dev_priv->depth_clear.rb3d_zstencilcntl =
1276 (dev_priv->depth_fmt |
1283 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1296 dev_priv->ring_offset = init->ring_offset;
1297 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1298 dev_priv->buffers_offset = init->buffers_offset;
1299 dev_priv->gart_textures_offset = init->gart_textures_offset;
1308 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1309 if (!dev_priv->cp_ring) {
1314 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1315 if (!dev_priv->ring_rptr) {
1329 dev_priv->gart_textures =
1331 if (!dev_priv->gart_textures) {
1339 if (dev_priv->flags & RADEON_IS_AGP) {
1340 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1341 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1343 if (!dev_priv->cp_ring->handle ||
1344 !dev_priv->ring_rptr->handle ||
1353 dev_priv->cp_ring->handle =
1354 (void *)(unsigned long)dev_priv->cp_ring->offset;
1355 dev_priv->ring_rptr->handle =
1356 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1360 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1361 dev_priv->cp_ring->handle);
1362 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1363 dev_priv->ring_rptr->handle);
1368 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1369 dev_priv->fb_size =
1370 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1371 - dev_priv->fb_location;
1373 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1374 ((dev_priv->front_offset
1375 + dev_priv->fb_location) >> 10));
1377 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1378 ((dev_priv->back_offset
1379 + dev_priv->fb_location) >> 10));
1381 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1382 ((dev_priv->depth_offset
1383 + dev_priv->fb_location) >> 10));
1385 dev_priv->gart_size = init->gart_size;
1388 if (dev_priv->new_memmap) {
1398 if (dev_priv->flags & RADEON_IS_AGP) {
1401 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1402 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1411 base = dev_priv->fb_location + dev_priv->fb_size;
1412 if (base < dev_priv->fb_location ||
1413 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1414 base = dev_priv->fb_location
1415 - dev_priv->gart_size;
1417 dev_priv->gart_vm_start = base & 0xffc00000u;
1418 if (dev_priv->gart_vm_start != base)
1420 base, dev_priv->gart_vm_start);
1423 dev_priv->gart_vm_start = dev_priv->fb_location +
1428 if (dev_priv->flags & RADEON_IS_AGP)
1429 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1431 + dev_priv->gart_vm_start);
1434 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1436 + dev_priv->gart_vm_start);
1438 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1439 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1440 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1441 dev_priv->gart_buffers_offset);
1443 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1444 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1446 dev_priv->ring.size = init->ring_size;
1447 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1449 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1450 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1452 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1453 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1454 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1456 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1459 if (dev_priv->flags & RADEON_IS_AGP) {
1461 radeon_set_pcigart(dev_priv, 0);
1468 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1470 if (dev_priv->pcigart_offset_set) {
1471 dev_priv->gart_info.bus_addr =
1472 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1473 dev_priv->gart_info.mapping.offset =
1474 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1475 dev_priv->gart_info.mapping.size =
1476 dev_priv->gart_info.table_size;
1478 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1479 dev_priv->gart_info.addr =
1480 dev_priv->gart_info.mapping.handle;
1482 if (dev_priv->flags & RADEON_IS_PCIE)
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1485 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1486 dev_priv->gart_info.gart_table_location =
1490 dev_priv->gart_info.addr,
1491 dev_priv->pcigart_offset);
1493 if (dev_priv->flags & RADEON_IS_IGPGART)
1494 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1496 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1497 dev_priv->gart_info.gart_table_location =
1499 dev_priv->gart_info.addr = NULL;
1500 dev_priv->gart_info.bus_addr = 0;
1501 if (dev_priv->flags & RADEON_IS_PCIE) {
1511 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1514 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1523 ret = radeon_setup_pcigart_surface(dev_priv);
1526 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1527 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1529 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1535 radeon_set_pcigart(dev_priv, 1);
1538 if (!dev_priv->me_fw) {
1539 int err = radeon_cp_init_microcode(dev_priv);
1546 radeon_cp_load_microcode(dev_priv);
1547 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1549 dev_priv->last_buf = 0;
1552 radeon_test_writeback(dev_priv);
1559 drm_radeon_private_t *dev_priv = dev->dev_private;
1570 if (dev_priv->flags & RADEON_IS_AGP) {
1571 if (dev_priv->cp_ring != NULL) {
1572 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1573 dev_priv->cp_ring = NULL;
1575 if (dev_priv->ring_rptr != NULL) {
1576 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1577 dev_priv->ring_rptr = NULL;
1587 if (dev_priv->gart_info.bus_addr) {
1589 radeon_set_pcigart(dev_priv, 0);
1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1591 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1593 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1598 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1600 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1601 dev_priv->gart_info.addr = NULL;
1605 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1619 drm_radeon_private_t *dev_priv = dev->dev_private;
1621 if (!dev_priv) {
1629 if (dev_priv->flags & RADEON_IS_AGP) {
1631 radeon_set_pcigart(dev_priv, 0);
1636 radeon_set_pcigart(dev_priv, 1);
1639 radeon_cp_load_microcode(dev_priv);
1640 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1642 dev_priv->have_z_offset = 0;
1653 drm_radeon_private_t *dev_priv = dev->dev_private;
1669 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1680 drm_radeon_private_t *dev_priv = dev->dev_private;
1685 if (dev_priv->cp_running) {
1689 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1691 dev_priv->cp_mode);
1695 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1696 r600_do_cp_start(dev_priv);
1698 radeon_do_cp_start(dev_priv);
1708 drm_radeon_private_t *dev_priv = dev->dev_private;
1715 if (!dev_priv->cp_running)
1722 radeon_do_cp_flush(dev_priv);
1729 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1730 ret = r600_do_cp_idle(dev_priv);
1732 ret = radeon_do_cp_idle(dev_priv);
1741 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742 r600_do_cp_stop(dev_priv);
1744 radeon_do_cp_stop(dev_priv);
1747 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1757 drm_radeon_private_t *dev_priv = dev->dev_private;
1760 if (dev_priv) {
1761 if (dev_priv->cp_running) {
1763 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1764 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1773 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1782 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1783 r600_do_cp_stop(dev_priv);
1786 radeon_do_cp_stop(dev_priv);
1791 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1793 if (dev_priv->mmio) /* remove this after permanent addmaps */
1796 if (dev_priv->mmio) { /* remove all surfaces */
1808 radeon_mem_takedown(&(dev_priv->gart_heap));
1809 radeon_mem_takedown(&(dev_priv->fb_heap));
1812 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1816 if (dev_priv->me_fw != NULL) {
1817 firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
1818 dev_priv->me_fw = NULL;
1820 if (dev_priv->pfp_fw != NULL) {
1821 firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
1822 dev_priv->pfp_fw = NULL;
1831 drm_radeon_private_t *dev_priv = dev->dev_private;
1836 if (!dev_priv) {
1841 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1842 r600_do_cp_reset(dev_priv);
1844 radeon_do_cp_reset(dev_priv);
1847 dev_priv->cp_running = 0;
1854 drm_radeon_private_t *dev_priv = dev->dev_private;
1859 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1860 return r600_do_cp_idle(dev_priv);
1862 return radeon_do_cp_idle(dev_priv);
1869 drm_radeon_private_t *dev_priv = dev->dev_private;
1872 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1880 drm_radeon_private_t *dev_priv = dev->dev_private;
1885 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1926 drm_radeon_private_t *dev_priv = dev->dev_private;
1932 if (++dev_priv->last_buf >= dma->buf_count)
1933 dev_priv->last_buf = 0;
1935 start = dev_priv->last_buf;
1937 for (t = 0; t < dev_priv->usec_timeout; t++) {
1938 u32 done_age = GET_SCRATCH(dev_priv, 1);
1946 dev_priv->stats.requested_bufs++;
1956 dev_priv->stats.freelist_loops++;
1966 drm_radeon_private_t *dev_priv = dev->dev_private;
1969 dev_priv->last_buf = 0;
1981 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1983 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1985 u32 last_head = GET_RING_HEAD(dev_priv);
1987 for (i = 0; i < dev_priv->usec_timeout; i++) {
1988 u32 head = GET_RING_HEAD(dev_priv);
1996 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2007 radeon_status(dev_priv);
2074 drm_radeon_private_t *dev_priv;
2077 dev_priv = malloc(sizeof(drm_radeon_private_t),
2079 if (dev_priv == NULL)
2082 dev->dev_private = (void *)dev_priv;
2083 dev_priv->flags = flags;
2098 dev_priv->flags |= RADEON_HAS_HIERZ;
2108 dev_priv->flags |= RADEON_IS_AGP;
2110 dev_priv->flags |= RADEON_IS_PCIE;
2112 dev_priv->flags |= RADEON_IS_PCI;
2116 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2127 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2186 drm_radeon_private_t *dev_priv = dev->dev_private;
2188 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2190 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2191 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2202 drm_radeon_private_t *dev_priv = dev->dev_private;
2206 drm_rmmap(dev, dev_priv->mmio);
2208 free(dev_priv, DRM_MEM_DRIVER);
2214 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2222 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2226 ring = dev_priv->ring.start;
2229 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2231 dev_priv->ring.tail += i;
2233 dev_priv->ring.space -= num_p2 * sizeof(u32);
2236 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2239 GET_RING_HEAD( dev_priv );
2241 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2242 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2246 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);