drm2/radeon/r600.c

4144 	u32 link_width_cntl, mask, target_reg;
4183 	link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4185 	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4189 	if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4192 	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4196 	link_width_cntl |= mask;
4198 	WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4204         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4205 		link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4207 		link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4209 	WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4218         link_width_cntl = RREG32(target_reg);
4219         while (link_width_cntl == 0xffffffff)
4220 		link_width_cntl = RREG32(target_reg);
4226 	u32 link_width_cntl;
4240 	link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4242 	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4261 	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4303 		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4304 		link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4305 		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4306 		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4307 		if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4308 			lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4309 			link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4311 			link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4312 			WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4314 			link_width_cntl |= LC_UPCONFIGURE_DIS;
4315 			WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4368 		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4371 			link_width_cntl |= LC_UPCONFIGURE_DIS;
4373 			link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4374 		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);