Lines Matching refs:gb_addr_config
468 u32 gb_addr_config = 0;
501 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
563 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
592 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
594 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
596 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
598 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
600 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
602 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
606 /* setup tiling info dword. gb_addr_config is not adequate since it does
648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
650 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
668 WREG32(GB_ADDR_CONFIG, gb_addr_config);
669 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
671 WREG32(DMIF_ADDR_CALC, gb_addr_config);
672 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
673 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
674 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
686 tmp = gb_addr_config & NUM_PIPES_MASK;