Lines Matching defs:idx_value
1998 u32 idx_value;
2003 idx_value = radeon_get_ib_value(p, idx);
2036 (idx_value & 0xfffffff0) +
2082 idx_value +
2109 idx_value +
2226 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2239 if (idx_value & 0x10) {
2439 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2455 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2475 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2578 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2588 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2598 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2612 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2627 if (idx_value & 0x1) {
2646 if (((idx_value >> 1) & 0x3) == 2) {
2699 if (idx_value & 0x1) {
2723 if (idx_value & 0x2) {
2894 u32 idx, idx_value;
2951 idx_value = radeon_get_ib_value(p, idx + 2);
2956 if (idx_value & (1U << 31)) {
2999 if (idx_value & (1U << 31)) {
3016 if (idx_value & (1U << 31)) {
3055 if (idx_value & (1U << 31)) {
3100 if (idx_value & (1U << 31)) {
3144 if (idx_value & (1U << 31)) {
3445 u32 idx_value = ib[idx];
3494 if (idx_value & 0x100) {
3501 if (idx_value & 0x2) {
3508 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3540 start_reg = idx_value << 2;