drm2/i915/intel_display.c

50 	int p1, p2;
70 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
115 	.p1 = { .min = 2, .max = 33 },
129 	.p1 = { .min = 1, .max = 6 },
143 	.p1 = { .min = 1, .max = 8 },
157 	.p1 = { .min = 1, .max = 8 },
172 	.p1 = { .min = 1, .max = 3},
188 	.p1 = { .min = 1, .max = 8},
202 	.p1 = { .min = 2, .max = 8 },
217 	.p1 = { .min = 2, .max = 6 },
232 	.p1 = { .min = 1, .max = 2},
248 	.p1 = { .min = 1, .max = 8 },
262 	.p1 = { .min = 1, .max = 8 },
281 	.p1 = { .min = 1, .max = 8 },
295 	.p1 = { .min = 2, .max = 8 },
309 	.p1 = { .min = 2, .max = 8 },
324 	.p1 = { .min = 2, .max = 8 },
338 	.p1 = { .min = 2, .max = 6 },
352 	.p1 = { .min = 1, .max = 2},
549 	clock->p = clock->p1 * clock->p2;
561 	clock->p = clock->p1 * clock->p2;
592 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
593 		INTELPllInvalid("p1 out of range\n");
658 				for (clock.p1 = limit->p1.min;
659 					clock.p1 <= limit->p1.max; clock.p1++) {
725 				for (clock.p1 = limit->p1.max;
726 				     clock.p1 >= limit->p1.min; clock.p1--) {
761 		clock.p1 = 2;
767 		clock.p1 = 1;
785 		clock.p1 = 2;
791 		clock.p1 = 1;
798 	clock.p = (clock.p1 * clock.p2);
3724 		clock->p1 = 2;
3731 		clock->p1 = 1;
3851 	/* compute bitmask from p1 value */
3853 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3855 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3857 			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3943 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3945 		if (clock->p1 == 2)
3948 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4040 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4410 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4441 			clock.p1 = 2;
4448 			clock.p1 = 1;
4561 	/* compute bitmask from p1 value */
4562 	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564 	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5575 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5578 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5602 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5614 				clock.p1 = 2;
5616 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>