drm2/i915/intel_display.c

932 			   struct intel_crtc *intel_crtc, bool state)
943 	if (!intel_crtc->pch_pll) {
954 		KASSERT(((pch_dpll >> (4 * intel_crtc->pipe)) & 8) != 0,
955 		    ("transcoder %d PLL not enabled\n", intel_crtc->pipe));
958 	reg = intel_crtc->pch_pll->pll_reg;
1424 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1426 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1433 	pll = intel_crtc->pch_pll;
1444 		      intel_crtc->base.base.id);
1450 		assert_pch_pll_enabled(dev_priv, intel_crtc);
1466 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1468 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1469 	struct intel_pch_pll *pll = intel_crtc->pch_pll;
1485 		      intel_crtc->base.base.id);
1489 		assert_pch_pll_disabled(dev_priv, intel_crtc);
1494 		assert_pch_pll_enabled(dev_priv, intel_crtc);
1501 	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1851 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1854 	int plane = intel_crtc->plane;
1924 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1927 	int plane = intel_crtc->plane;
2055 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2064 	if(intel_crtc->plane > dev_priv->num_pipe) {
2066 				intel_crtc->plane,
2093 		intel_wait_for_vblank(dev, intel_crtc->pipe);
2107 	if (intel_crtc->pipe) {
2159 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 	int pipe = intel_crtc->pipe;
2213 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 	int pipe = intel_crtc->pipe;
2215 	int plane = intel_crtc->plane;
2236 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2317 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318 	int pipe = intel_crtc->pipe;
2336 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2451 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2452 	int pipe = intel_crtc->pipe;
2470 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2561 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 	int pipe = intel_crtc->pipe;
2573 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2618 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619 	int pipe = intel_crtc->pipe;
2831 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832 	int pipe = intel_crtc->pipe;
2840 	intel_enable_pch_pll(intel_crtc);
2864 		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2926 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2928 	struct intel_pch_pll *pll = intel_crtc->pch_pll;
2939 	intel_crtc->pch_pll = NULL;
2942 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2944 	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2948 	pll = intel_crtc->pch_pll;
2951 			      intel_crtc->base.base.id, pll->pll_reg);
2957 		i = intel_crtc->pipe;
2961 			      intel_crtc->base.base.id, pll->pll_reg);
2976 				      intel_crtc->base.base.id,
2988 				      intel_crtc->base.base.id, pll->pll_reg);
2996 	intel_crtc->pch_pll = pll;
2998 	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3036 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 	int pipe = intel_crtc->pipe;
3038 	int plane = intel_crtc->plane;
3042 	if (intel_crtc->active)
3045 	intel_crtc->active = true;
3092 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093 	int pipe = intel_crtc->pipe;
3094 	int plane = intel_crtc->plane;
3097 	if (!intel_crtc->active)
3154 	intel_disable_pch_pll(intel_crtc);
3177 	intel_crtc->active = false;
3187 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 	int pipe = intel_crtc->pipe;
3189 	int plane = intel_crtc->plane;
3211 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 	intel_put_pch_pll(intel_crtc);
3215 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3217 	if (!enable && intel_crtc->overlay) {
3218 		struct drm_device *dev = intel_crtc->base.dev;
3223 		(void) intel_overlay_switch_off(intel_crtc->overlay);
3237 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3238 	int pipe = intel_crtc->pipe;
3239 	int plane = intel_crtc->plane;
3241 	if (intel_crtc->active)
3244 	intel_crtc->active = true;
3255 	intel_crtc_dpms_overlay(intel_crtc, true);
3263 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3264 	int pipe = intel_crtc->pipe;
3265 	int plane = intel_crtc->plane;
3267 	if (!intel_crtc->active)
3273 	intel_crtc_dpms_overlay(intel_crtc, false);
3283 	intel_crtc->active = false;
3317 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3318 	int pipe = intel_crtc->pipe;
3321 	if (intel_crtc->dpms_mode == mode)
3324 	intel_crtc->dpms_mode = mode;
3410 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3416 		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3745 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746 	int pipe = intel_crtc->pipe;
3763 	intel_crtc->lowfreq_avail = false;
3767 		intel_crtc->lowfreq_avail = true;
3778 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3779 	int pipe = intel_crtc->pipe;
3826 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 	int pipe = intel_crtc->pipe;
3936 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3937 	int pipe = intel_crtc->pipe;
3997 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3998 	int pipe = intel_crtc->pipe;
3999 	int plane = intel_crtc->plane;
4119 		if (intel_crtc->lowfreq_avail) {
4350 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351 	int pipe = intel_crtc->pipe;
4352 	int plane = intel_crtc->plane;
4507 	intel_crtc->bpp = pipe_bpp;
4516 		u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4520 	intel_crtc->fdi_lanes = lane;
4524 	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4608 		pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4615 		intel_put_pch_pll(intel_crtc);
4672 	if (intel_crtc->pch_pll) {
4673 		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4676 		POSTING_READ(intel_crtc->pch_pll->pll_reg);
4684 		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4687 	intel_crtc->lowfreq_avail = false;
4688 	if (intel_crtc->pch_pll) {
4690 			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4691 			intel_crtc->lowfreq_avail = true;
4697 			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4778 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4779 	int pipe = intel_crtc->pipe;
4789 		intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4791 		intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4977 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978 	int palreg = PALETTE(intel_crtc->pipe);
4982 	if (!crtc->enabled || !intel_crtc->active)
4987 		palreg = LGC_PALETTE(intel_crtc->pipe);
4991 			   (intel_crtc->lut_r[i] << 16) |
4992 			   (intel_crtc->lut_g[i] << 8) |
4993 			   intel_crtc->lut_b[i]);
5001 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005 	if (intel_crtc->cursor_visible == visible)
5024 	intel_crtc->cursor_visible = visible;
5031 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 	int pipe = intel_crtc->pipe;
5035 	if (intel_crtc->cursor_visible != visible) {
5047 		intel_crtc->cursor_visible = visible;
5057 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058 	int pipe = intel_crtc->pipe;
5061 	if (intel_crtc->cursor_visible != visible) {
5072 		intel_crtc->cursor_visible = visible;
5084 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5085 	int pipe = intel_crtc->pipe;
5086 	int x = intel_crtc->cursor_x;
5087 	int y = intel_crtc->cursor_y;
5094 		base = intel_crtc->cursor_addr;
5104 		if (x + intel_crtc->cursor_width < 0)
5113 		if (y + intel_crtc->cursor_height < 0)
5122 	if (!visible && !intel_crtc->cursor_visible)
5144 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201 						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5214 	if (intel_crtc->cursor_bo) {
5216 			if (intel_crtc->cursor_bo != obj)
5217 				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5219 			i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
5220 		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5225 	intel_crtc->cursor_addr = addr;
5226 	intel_crtc->cursor_bo = obj;
5227 	intel_crtc->cursor_width = width;
5228 	intel_crtc->cursor_height = height;
5244 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246 	intel_crtc->cursor_x = x;
5247 	intel_crtc->cursor_y = y;
5258 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5260 	intel_crtc->lut_r[regno] = red >> 8;
5261 	intel_crtc->lut_g[regno] = green >> 8;
5262 	intel_crtc->lut_b[regno] = blue >> 8;
5268 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5270 	*red = intel_crtc->lut_r[regno] << 8;
5271 	*green = intel_crtc->lut_g[regno] << 8;
5272 	*blue = intel_crtc->lut_b[regno] << 8;
5279 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5282 		intel_crtc->lut_r[i] = red[i] >> 8;
5283 		intel_crtc->lut_g[i] = green[i] >> 8;
5284 		intel_crtc->lut_b[i] = blue[i] >> 8;
5406 	struct intel_crtc *intel_crtc;
5432 		intel_crtc = to_intel_crtc(crtc);
5433 		old->dpms_mode = intel_crtc->dpms_mode;
5437 		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5473 	intel_crtc = to_intel_crtc(crtc);
5474 	old->dpms_mode = intel_crtc->dpms_mode;
5513 	intel_wait_for_vblank(dev, intel_crtc->pipe);
5553 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5554 	int pipe = intel_crtc->pipe;
5641 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642 	int pipe = intel_crtc->pipe;
5688 	struct intel_crtc *intel_crtc = arg;
5689 	struct drm_crtc *crtc = &intel_crtc->base;
5696 		callout_schedule(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT);
5700 	intel_crtc->busy = false;
5708 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5709 	int pipe = intel_crtc->pipe;
5735 	callout_reset(&intel_crtc->idle_callout, CRTC_IDLE_TIMEOUT,
5736 	    intel_crtc_idle_timer, intel_crtc);
5743 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5755 	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5756 		int pipe = intel_crtc->pipe;
5786 	struct intel_crtc *intel_crtc;
5800 		intel_crtc = to_intel_crtc(crtc);
5801 		if (!intel_crtc->busy)
5823 	struct intel_crtc *intel_crtc;
5842 		intel_crtc = to_intel_crtc(crtc);
5845 			if (!intel_crtc->busy) {
5848 				intel_crtc->busy = true;
5851 				callout_reset(&intel_crtc->idle_callout,
5853 				    intel_crtc);
5861 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5867 	work = intel_crtc->unpin_work;
5868 	intel_crtc->unpin_work = NULL;
5879 	free(intel_crtc, DRM_MEM_KMS);
5902 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5909 	if (intel_crtc == NULL)
5915 	work = intel_crtc->unpin_work;
5921 	intel_crtc->unpin_work = NULL;
5925 		e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5954 	drm_vblank_put(dev, intel_crtc->pipe);
5958 	atomic_clear_int(&obj->pending_flip, 1 << intel_crtc->plane);
5965 	CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
5988 	struct intel_crtc *intel_crtc =
5992 	if (intel_crtc->unpin_work) {
5993 		if ((++intel_crtc->unpin_work->pending) > 1)
6007 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6027 	if (intel_crtc->plane)
6034 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6053 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 	if (intel_crtc->plane)
6077 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6097 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6115 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6124 	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6141 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6163 	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6166 	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6189 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6201 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6230 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6242 	ret = drm_vblank_get(dev, intel_crtc->pipe);
6248 	if (intel_crtc->unpin_work) {
6251 		drm_vblank_put(dev, intel_crtc->pipe);
6256 	intel_crtc->unpin_work = work;
6277 	atomic_set_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6286 	CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
6291 	atomic_clear_int(&work->old_fb_obj->pending_flip, 1 << intel_crtc->plane);
6297 	intel_crtc->unpin_work = NULL;
6300 	drm_vblank_put(dev, intel_crtc->pipe);
6353 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 	intel_crtc->dpms_mode = -1;
6363 	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6406 	struct intel_crtc *intel_crtc;
6409 	intel_crtc = malloc(sizeof(struct intel_crtc) +
6413 	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6415 	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6417 		intel_crtc->lut_r[i] = i;
6418 		intel_crtc->lut_g[i] = i;
6419 		intel_crtc->lut_b[i] = i;
6423 	intel_crtc->pipe = pipe;
6424 	intel_crtc->plane = pipe;
6427 		intel_crtc->plane = !pipe;
6431 	    dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
6433 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6434 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6436 	intel_crtc_reset(&intel_crtc->base);
6437 	intel_crtc->active = true; /* force the pipe off on setup_init_config */
6438 	intel_crtc->bpp = 24; /* default for pre-Ironlake */
6448 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6450 	intel_crtc->busy = false;
6452 	callout_init(&intel_crtc->idle_callout, CALLOUT_MPSAFE);
6460 	struct intel_crtc *crtc;
7055 	struct intel_crtc *intel_crtc;
7069 		intel_crtc = to_intel_crtc(crtc);
7099 		intel_crtc = to_intel_crtc(crtc);
7100 		callout_drain(&intel_crtc->idle_callout);