drm2/i915/i915_gem_gtt.c

77 	struct drm_i915_private *dev_priv;
81 	dev_priv = dev->dev_private;
101 			dev_priv->mm.aliasing_ppgtt = ppgtt;
107 	ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt.scratch_page_dma;
112 	dev_priv->mm.aliasing_ppgtt = ppgtt;
160 	struct drm_i915_private *dev_priv;
164 	dev_priv = dev->dev_private;
195 	struct drm_i915_private *dev_priv;
200 	dev_priv = dev->dev_private;
201 	ppgtt = dev_priv->mm.aliasing_ppgtt;
204 	dev_priv->mm.aliasing_ppgtt = NULL;
242 do_idling(struct drm_i915_private *dev_priv)
244 	bool ret = dev_priv->mm.interruptible;
246 	if (dev_priv->mm.gtt.do_idle_maps) {
247 		dev_priv->mm.interruptible = false;
248 		if (i915_gpu_idle(dev_priv->dev)) {
259 undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
262 	if (dev_priv->mm.gtt.do_idle_maps)
263 		dev_priv->mm.interruptible = interruptible;
269 	struct drm_i915_private *dev_priv;
272 	dev_priv = dev->dev_private;
275 	intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
276 	    (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
278 	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
298 	struct drm_i915_private *dev_priv;
302 	dev_priv = dev->dev_private;
325 	struct drm_i915_private *dev_priv = dev->dev_private;
329 	dev_priv = dev->dev_private;
331 	interruptible = do_idling(dev_priv);
333 	undo_idling(dev_priv, interruptible);
340 	drm_i915_private_t *dev_priv;
344 	dev_priv = dev->dev_private;
348 	drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
350 	dev_priv->mm.gtt_start = start;
351 	dev_priv->mm.gtt_mappable_end = mappable_end;
352 	dev_priv->mm.gtt_end = end;
353 	dev_priv->mm.gtt_total = end - start;
354 	dev_priv->mm.mappable_gtt_total = mappable;