drm2/i915/i915_dma.c

42 	intel_ring_begin(LP_RING(dev_priv), (n))
45 	intel_ring_emit(LP_RING(dev_priv), x)
48 	intel_ring_advance(LP_RING(dev_priv))
56 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
58 	if (I915_NEED_GFX_HWS(dev_priv->dev))
59 		return ((volatile u32*)(dev_priv->dri1.gfx_hws_cpu_addr))[reg];
61 		return intel_read_status_page(LP_RING(dev_priv), reg);
64 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
65 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
70 	drm_i915_private_t *dev_priv = dev->dev_private;
77 				READ_BREADCRUMB(dev_priv);
83 	drm_i915_private_t *dev_priv = dev->dev_private;
86 	addr = dev_priv->status_page_dmah->busaddr;
88 		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
98 	drm_i915_private_t *dev_priv = dev->dev_private;
99 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
107 	dev_priv->status_page_dmah =
109 	if (!dev_priv->status_page_dmah) {
113 	ring->status_page.page_addr = dev_priv->hw_status_page =
114 	    dev_priv->status_page_dmah->vaddr;
115 	dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
117 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
121 	    (uintmax_t)dev_priv->dma_status_page);
131 	drm_i915_private_t *dev_priv = dev->dev_private;
132 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
134 	if (dev_priv->status_page_dmah) {
135 		drm_pci_free(dev, dev_priv->status_page_dmah);
136 		dev_priv->status_page_dmah = NULL;
139 	if (dev_priv->status_gfx_addr) {
140 		dev_priv->status_gfx_addr = 0;
142 		pmap_unmapdev((vm_offset_t)dev_priv->dri1.gfx_hws_cpu_addr,
152 	drm_i915_private_t *dev_priv = dev->dev_private;
154 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
179 	drm_i915_private_t *dev_priv = dev->dev_private;
192 		intel_cleanup_ring_buffer(&dev_priv->rings[i]);
204 	drm_i915_private_t *dev_priv = dev->dev_private;
217 		if (LP_RING(dev_priv)->obj != NULL) {
233 	dev_priv->cpp = init->cpp;
234 	dev_priv->back_offset = init->back_offset;
235 	dev_priv->front_offset = init->front_offset;
236 	dev_priv->current_page = 0;
242 	dev_priv->dri1.allow_batchbuffer = 1;
249 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
250 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
382 	drm_i915_private_t *dev_priv = dev->dev_private;
385 	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
435 	drm_i915_private_t *dev_priv = dev->dev_private;
477 	drm_i915_private_t *dev_priv = dev->dev_private;
480 	if (++dev_priv->counter > 0x7FFFFFFFUL)
481 		dev_priv->counter = 0;
483 		master_priv->sarea_priv->last_enqueue = dev_priv->counter;
488 		OUT_RING(dev_priv->counter);
530 	drm_i915_private_t *dev_priv = dev->dev_private;
587 	drm_i915_private_t *dev_priv = dev->dev_private;
597 		  dev_priv->current_page,
610 	if (dev_priv->current_page == 0) {
611 		OUT_RING(dev_priv->back_offset);
612 		dev_priv->current_page = 1;
614 		OUT_RING(dev_priv->front_offset);
615 		dev_priv->current_page = 0;
624 	master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
629 		OUT_RING(dev_priv->counter);
634 	master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
667 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
676 	if (!dev_priv->dri1.allow_batchbuffer) {
705 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
715 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
759 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
770 	drm_i915_private_t *dev_priv = dev->dev_private;
777 	dev_priv->counter++;
778 	if (dev_priv->counter > 0x7FFFFFFFUL)
779 		dev_priv->counter = 1;
781 		master_priv->sarea_priv->last_enqueue = dev_priv->counter;
786 		OUT_RING(dev_priv->counter);
791 	return dev_priv->counter;
796 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
799 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
802 		  READ_BREADCRUMB(dev_priv));
804 	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
806 			master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
814 	mtx_lock(&dev_priv->irq_lock);
816 		while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) {
817 			ret = -msleep(ring, &dev_priv->irq_lock, PCATCH,
823 		mtx_unlock(&dev_priv->irq_lock);
825 		mtx_unlock(&dev_priv->irq_lock);
826 		if (_intel_wait_for(dev, READ_BREADCRUMB(dev_priv) >= irq_nr,
833 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
844 	drm_i915_private_t *dev_priv = dev->dev_private;
851 	if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
875 	drm_i915_private_t *dev_priv = dev->dev_private;
881 	if (!dev_priv) {
892 	drm_i915_private_t *dev_priv = dev->dev_private;
898 	if (!dev_priv) {
953 	drm_i915_private_t *dev_priv = dev->dev_private;
957 	if (!dev_priv) {
967 		value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
970 		value = READ_BREADCRUMB(dev_priv);
979 		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
982 		value = dev_priv->overlay ? 1 : 0;
991 		value = intel_ring_initialized(&dev_priv->rings[VCS]);
994 		value = intel_ring_initialized(&dev_priv->rings[BCS]);
1015 		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1034 	drm_i915_private_t *dev_priv = dev->dev_private;
1037 	if (!dev_priv) {
1048 		dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1051 		if (param->value > dev_priv->num_fence_regs ||
1055 		dev_priv->fence_reg_start = param->value;
1068 	drm_i915_private_t *dev_priv = dev->dev_private;
1070 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
1078 	if (!dev_priv) {
1089 	ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1092 	dev_priv->dri1.gfx_hws_cpu_addr = pmap_mapdev_attr(
1095 	if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1097 		ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1103 	memset(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1104 	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1106 			dev_priv->status_gfx_addr);
1107 	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1114 	struct drm_i915_private *dev_priv = dev->dev_private;
1153 	dev_priv->mm.suspended = 0;
1196 	struct drm_i915_private *dev_priv;
1198 	dev_priv = dev->dev_private;
1200 	dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1201 	if (dev_priv->bridge_dev == NULL) {
1219 	drm_i915_private_t *dev_priv;
1225 	dev_priv = dev->dev_private;
1229 		temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1232 	temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1244 	dev_priv->mch_res_rid = 0x100;
1245 	dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1246 	    dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1248 	if (dev_priv->mch_res == NULL) {
1254 		temp = rman_get_start(dev_priv->mch_res);
1256 		pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1258 	pci_write_config(dev_priv->bridge_dev, reg,
1259 	    rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1266 	drm_i915_private_t *dev_priv;
1271 	dev_priv = dev->dev_private;
1274 	dev_priv->mchbar_need_disable = false;
1277 		temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1280 		temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1293 	dev_priv->mchbar_need_disable = true;
1297 		pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1300 		temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1301 		pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1308 	drm_i915_private_t *dev_priv;
1313 	dev_priv = dev->dev_private;
1316 	if (dev_priv->mchbar_need_disable) {
1318 			temp = pci_read_config(dev_priv->bridge_dev,
1321 			pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1324 			temp = pci_read_config(dev_priv->bridge_dev,
1327 			pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1332 	if (dev_priv->mch_res != NULL) {
1335 		    SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1337 		    SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1338 		dev_priv->mch_res = NULL;
1345 	struct drm_i915_private *dev_priv = dev->dev_private;
1366 	dev_priv = malloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1369 	dev->dev_private = (void *)dev_priv;
1370 	dev_priv->dev = dev;
1371 	dev_priv->info = info;
1374 		free(dev_priv, DRM_MEM_DRIVER);
1377 	dev_priv->mm.gtt = intel_gtt_get();
1385 	    _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1388 		free(dev_priv, DRM_MEM_DRIVER);
1392 	dev_priv->tq = taskqueue_create("915", M_WAITOK,
1393 	    taskqueue_thread_enqueue, &dev_priv->tq);
1394 	taskqueue_start_threads(&dev_priv->tq, 1, PWAIT, "i915 taskq");
1395 	mtx_init(&dev_priv->gt_lock, "915gt", NULL, MTX_DEF);
1396 	mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF);
1397 	mtx_init(&dev_priv->error_completion_lock, "915cmp", NULL, MTX_DEF);
1398 	mtx_init(&dev_priv->rps_lock, "915rps", NULL, MTX_DEF);
1399 	mtx_init(&dev_priv->dpio_lock, "915dpi", NULL, MTX_DEF);
1429 			drm_rmmap(dev, dev_priv->mmio_map);
1430 			free(dev_priv, DRM_MEM_DRIVER);
1435 	mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF);
1438 		dev_priv->num_pipe = 3;
1440 		dev_priv->num_pipe = 2;
1442 		dev_priv->num_pipe = 1;
1444 	ret = drm_vblank_init(dev, dev_priv->num_pipe);
1449 	dev_priv->mm.suspended = 1;
1463 	callout_init(&dev_priv->hangcheck_timer, 1);
1464 	callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1468 		intel_gpu_ips_init(dev_priv);
1481 	struct drm_i915_private *dev_priv = dev->dev_private;
1501 	callout_stop(&dev_priv->hangcheck_timer);
1502 	callout_drain(&dev_priv->hangcheck_timer);
1524 		drm_mm_takedown(&dev_priv->mm.stolen);
1534 	mtx_destroy(&dev_priv->irq_lock);
1536 	if (dev_priv->tq != NULL)
1537 		taskqueue_free(dev_priv->tq);
1540 	drm_rmmap(dev, dev_priv->mmio_map);
1543 	mtx_destroy(&dev_priv->dpio_lock);
1544 	mtx_destroy(&dev_priv->error_lock);
1545 	mtx_destroy(&dev_priv->error_completion_lock);
1546 	mtx_destroy(&dev_priv->rps_lock);
1572 	drm_i915_private_t *dev_priv = dev->dev_private;
1574 	if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {