Lines Matching refs:dev_priv
43 dev_priv,
48 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
68 if (radeon_check_offset(dev_priv, off))
75 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
82 off = off - fb_end - 1 + dev_priv->gart_vm_start;
85 if (radeon_check_offset(dev_priv, off)) {
94 dev_priv,
101 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
109 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
122 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
132 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
147 if (radeon_check_and_fixup_offset(dev_priv,
163 if (radeon_check_and_fixup_offset(dev_priv,
268 dev_priv,
310 if (dev_priv->microcode_version != UCODE_R200) {
331 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
343 if (radeon_check_and_fixup_offset(dev_priv,
364 if (dev_priv->microcode_version != UCODE_R100) {
368 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
375 if (dev_priv->microcode_version != UCODE_R200) {
383 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) {
397 (dev_priv, file_priv, &offset)) {
408 (dev_priv, file_priv, &offset)) {
428 static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
446 static int radeon_emit_state(drm_radeon_private_t * dev_priv,
456 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
462 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
551 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
571 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
591 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
615 static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
629 return radeon_emit_state(dev_priv, file_priv, &state->context,
746 static void radeon_clear_box(drm_radeon_private_t * dev_priv,
752 x += dev_priv->sarea_priv->boxes[0].x1;
753 y += dev_priv->sarea_priv->boxes[0].y1;
755 switch (dev_priv->color_fmt) {
777 (dev_priv->color_fmt << 8) |
781 if (dev_priv->sarea_priv->pfCurrentPage == 1) {
782 OUT_RING(dev_priv->front_pitch_offset);
784 OUT_RING(dev_priv->back_pitch_offset);
795 static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv)
800 if (dev_priv->stats.last_frame_reads > 1 ||
801 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
802 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
805 if (dev_priv->stats.freelist_loops) {
806 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
811 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
812 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
816 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
817 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
824 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
825 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
829 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
830 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
835 if (dev_priv->stats.requested_bufs) {
836 if (dev_priv->stats.requested_bufs > 100)
837 dev_priv->stats.requested_bufs = 100;
839 radeon_clear_box(dev_priv, 4, 16,
840 dev_priv->stats.requested_bufs, 4,
844 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
856 drm_radeon_private_t *dev_priv = dev->dev_private;
857 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
858 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
867 dev_priv->stats.clears++;
913 (dev_priv->
919 OUT_RING(dev_priv->front_pitch_offset);
935 (dev_priv->
941 OUT_RING(dev_priv->back_pitch_offset);
959 dev_priv->depth_fmt ==
960 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
961 2) : (dev_priv->
974 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1019 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1020 && !(dev_priv->microcode_version == UCODE_R200)) {
1049 } else if (dev_priv->microcode_version == UCODE_R200) {
1103 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1104 && (dev_priv->microcode_version == UCODE_R200)
1124 else if ((dev_priv->microcode_version == UCODE_R200) &&
1226 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1297 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1345 drm_radeon_private_t *dev_priv = dev->dev_private;
1346 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1355 if (dev_priv->do_boxes)
1356 radeon_cp_performance_boxes(dev_priv);
1381 (dev_priv->color_fmt << 8) |
1391 OUT_RING(dev_priv->back_pitch_offset);
1392 OUT_RING(dev_priv->front_pitch_offset);
1394 OUT_RING(dev_priv->front_pitch_offset);
1395 OUT_RING(dev_priv->back_pitch_offset);
1422 drm_radeon_private_t *dev_priv = dev->dev_private;
1423 struct drm_sarea *sarea = (struct drm_sarea *)dev_priv->sarea->virtual;
1424 int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
1425 ? dev_priv->front_offset : dev_priv->back_offset;
1428 dev_priv->sarea_priv->pfCurrentPage);
1432 if (dev_priv->do_boxes) {
1433 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1434 radeon_cp_performance_boxes(dev_priv);
1443 ((sarea->frame.y * dev_priv->front_pitch +
1444 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1446 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1455 dev_priv->sarea_priv->last_frame++;
1456 dev_priv->sarea_priv->pfCurrentPage =
1457 1 - dev_priv->sarea_priv->pfCurrentPage;
1461 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1502 drm_radeon_private_t *dev_priv = dev->dev_private;
1503 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1504 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1523 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1546 drm_radeon_private_t *dev_priv = dev->dev_private;
1550 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1553 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1570 drm_radeon_private_t *dev_priv = dev->dev_private;
1575 int offset = (dev_priv->gart_buffers_offset
1605 drm_radeon_private_t *dev_priv = dev->dev_private;
1606 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1607 int offset = dev_priv->gart_buffers_offset + prim->offset;
1647 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1664 drm_radeon_private_t *dev_priv = dev->dev_private;
1676 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
1681 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1739 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1771 radeon_do_cp_idle(dev_priv);
1861 offset = dev_priv->gart_buffers_offset + buf->offset;
1904 drm_radeon_private_t *dev_priv = dev->dev_private;
1923 drm_radeon_private_t *dev_priv)
1925 if (!dev_priv->mmio)
1928 radeon_do_cp_idle(dev_priv);
1931 dev_priv->surfaces[surf_index].flags);
1933 dev_priv->surfaces[surf_index].lower);
1935 dev_priv->surfaces[surf_index].upper);
1950 drm_radeon_private_t *dev_priv,
1970 if ((dev_priv->surfaces[i].refcount != 0) &&
1971 (((new_lower >= dev_priv->surfaces[i].lower) &&
1972 (new_lower < dev_priv->surfaces[i].upper)) ||
1973 ((new_lower < dev_priv->surfaces[i].lower) &&
1974 (new_upper > dev_priv->surfaces[i].lower)))) {
1981 if (dev_priv->virt_surfaces[i].file_priv == 0)
1991 if ((dev_priv->surfaces[i].refcount == 1) &&
1992 (new->flags == dev_priv->surfaces[i].flags) &&
1993 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1994 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2000 dev_priv->surfaces[i].refcount++;
2001 dev_priv->surfaces[i].lower = s->lower;
2002 radeon_apply_surface_regs(s->surface_index, dev_priv);
2007 if ((dev_priv->surfaces[i].refcount == 1) &&
2008 (new->flags == dev_priv->surfaces[i].flags) &&
2009 (new_lower == dev_priv->surfaces[i].upper + 1)) {
2010 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2016 dev_priv->surfaces[i].refcount++;
2017 dev_priv->surfaces[i].upper = s->upper;
2018 radeon_apply_surface_regs(s->surface_index, dev_priv);
2025 if (dev_priv->surfaces[i].refcount == 0) {
2026 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2032 dev_priv->surfaces[i].refcount = 1;
2033 dev_priv->surfaces[i].lower = s->lower;
2034 dev_priv->surfaces[i].upper = s->upper;
2035 dev_priv->surfaces[i].flags = s->flags;
2036 radeon_apply_surface_regs(s->surface_index, dev_priv);
2046 drm_radeon_private_t * dev_priv,
2053 s = &(dev_priv->virt_surfaces[i]);
2057 if (dev_priv->surfaces[s->surface_index].
2059 dev_priv->surfaces[s->surface_index].
2062 if (dev_priv->surfaces[s->surface_index].
2064 dev_priv->surfaces[s->surface_index].
2067 dev_priv->surfaces[s->surface_index].refcount--;
2068 if (dev_priv->surfaces[s->surface_index].
2070 dev_priv->surfaces[s->surface_index].
2074 dev_priv);
2083 drm_radeon_private_t * dev_priv)
2087 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2088 free_surface(file_priv, dev_priv,
2089 dev_priv->virt_surfaces[i].lower);
2098 drm_radeon_private_t *dev_priv = dev->dev_private;
2101 if (alloc_surface(alloc, dev_priv, file_priv) == -1)
2109 drm_radeon_private_t *dev_priv = dev->dev_private;
2112 if (free_surface(file_priv, dev_priv, memfree->address))
2120 drm_radeon_private_t *dev_priv = dev->dev_private;
2121 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2128 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2147 drm_radeon_private_t *dev_priv = dev->dev_private;
2162 dev_priv->page_flipping = 1;
2164 if (dev_priv->sarea_priv->pfCurrentPage != 1)
2165 dev_priv->sarea_priv->pfCurrentPage = 0;
2175 drm_radeon_private_t *dev_priv = dev->dev_private;
2180 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2182 if (!dev_priv->page_flipping)
2193 drm_radeon_private_t *dev_priv = dev->dev_private;
2194 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2200 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2205 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2217 drm_radeon_private_t *dev_priv = dev->dev_private;
2226 sarea_priv = dev_priv->sarea_priv;
2241 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2242 VB_AGE_TEST_WITH_RETURN(dev_priv);
2262 if (radeon_emit_state(dev_priv, file_priv,
2295 drm_radeon_private_t *dev_priv = dev->dev_private;
2305 sarea_priv = dev_priv->sarea_priv;
2321 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2322 VB_AGE_TEST_WITH_RETURN(dev_priv);
2351 if (radeon_emit_state(dev_priv, file_priv,
2385 drm_radeon_private_t *dev_priv = dev->dev_private;
2402 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2403 VB_AGE_TEST_WITH_RETURN(dev_priv);
2405 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2415 drm_radeon_private_t *dev_priv = dev->dev_private;
2424 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2434 drm_radeon_private_t *dev_priv = dev->dev_private;
2442 if (!dev_priv) {
2475 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2476 VB_AGE_TEST_WITH_RETURN(dev_priv);
2484 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2505 drm_radeon_private_t *dev_priv = dev->dev_private;
2515 sarea_priv = dev_priv->sarea_priv;
2526 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2527 VB_AGE_TEST_WITH_RETURN(dev_priv);
2560 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
2597 static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2618 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) {
2633 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2655 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2675 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2697 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2727 drm_radeon_private_t *dev_priv = dev->dev_private;
2734 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2754 drm_radeon_private_t *dev_priv = dev->dev_private;
2764 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2794 radeon_emit_clip_rect(dev_priv, &box);
2813 drm_radeon_private_t *dev_priv = dev->dev_private;
2842 drm_radeon_private_t *dev_priv = dev->dev_private;
2853 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2854 VB_AGE_TEST_WITH_RETURN(dev_priv);
2879 if (dev_priv->microcode_version == UCODE_R300) {
2900 (dev_priv, file_priv, header, cmdbuf)) {
2908 if (radeon_emit_scalars(dev_priv, header, cmdbuf)) {
2916 if (radeon_emit_vectors(dev_priv, header, cmdbuf)) {
2961 if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) {
2976 if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) {
3005 drm_radeon_private_t *dev_priv = dev->dev_private;
3013 value = dev_priv->gart_buffers_offset;
3016 dev_priv->stats.last_frame_reads++;
3017 value = GET_SCRATCH(dev_priv, 0);
3020 value = GET_SCRATCH(dev_priv, 1);
3023 dev_priv->stats.last_clear_reads++;
3024 value = GET_SCRATCH(dev_priv, 2);
3027 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3033 value = dev_priv->gart_vm_start;
3036 value = dev_priv->mmio->offset;
3039 value = dev_priv->ring_rptr_offset;
3057 value = dev_priv->gart_textures_offset;
3060 if (!dev_priv->writeback_works)
3062 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3068 if (dev_priv->flags & RADEON_IS_PCIE)
3070 else if (dev_priv->flags & RADEON_IS_AGP)
3079 value = radeon_read_fb_location(dev_priv);
3082 value = dev_priv->num_gb_pipes;
3085 value = dev_priv->num_z_pipes;
3102 drm_radeon_private_t *dev_priv = dev->dev_private;
3109 radeon_priv->radeon_fb_delta = dev_priv->fb_location -
3115 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3116 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3117 if (dev_priv->sarea_priv)
3118 dev_priv->sarea_priv->tiling_enabled = 0;
3121 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3122 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3123 if (dev_priv->sarea_priv)
3124 dev_priv->sarea_priv->tiling_enabled = 1;
3128 dev_priv->pcigart_offset = sp->value;
3129 dev_priv->pcigart_offset_set = 1;
3132 dev_priv->new_memmap = sp->value;
3135 dev_priv->gart_info.table_size = sp->value;
3136 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3137 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3160 drm_radeon_private_t *dev_priv = dev->dev_private;
3161 dev_priv->page_flipping = 0;
3162 radeon_mem_release(file_priv, dev_priv->gart_heap);
3163 radeon_mem_release(file_priv, dev_priv->fb_heap);
3164 radeon_surfaces_release(file_priv, dev_priv);
3172 drm_radeon_private_t *dev_priv = dev->dev_private;
3174 if (dev_priv->sarea_priv &&
3175 dev_priv->sarea_priv->pfCurrentPage != 0)
3184 drm_radeon_private_t *dev_priv = dev->dev_private;
3197 if (dev_priv)
3198 radeon_priv->radeon_fb_delta = dev_priv->fb_location;