Lines Matching refs:T5
120 /* T5 bus driver interface */
136 /* T5 port (cxl) interface */
160 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
180 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
181 * T5 are under hw.cxl.
1635 /* T5 uses the relative offset inside the PCIe BAR */
2076 .fw_ver = htobe32_const(FW_VERSION(T5)),
2077 .intfver_nic = FW_INTFVER(T5, NIC),
2078 .intfver_vnic = FW_INTFVER(T5, VNIC),
2079 .intfver_ofld = FW_INTFVER(T5, OFLD),
2080 .intfver_ri = FW_INTFVER(T5, RI),
2081 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2082 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2083 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2084 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5355 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
8396 sx_init(&t4_list_lock, "T4/T5 adapters");
8399 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");