ulp/iw_cxgb/iw_cxgb_hal.c

94 cxio_rdma_cq_setup(struct cxio_rdev *rdev_p, unsigned id, uint64_t base_addr,
97 	struct adapter *sc = rdev_p->adap;
109 cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
115 	struct adapter *sc = rdev_p->adap;
153 				struct adapter *sc = rdev_p->adap;
169 cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
172 	return (cxio_rdma_cq_setup(rdev_p, cqid, 0, 0, 0, 0, 0));
176 cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
193 	return t3_offload_tx(rdev_p->adap, m);
197 cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
202 	cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
221 	return (cxio_rdma_cq_setup(rdev_p, cq->cqid, cq->dma_addr,
226 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
240 		qpid = cxio_hal_get_qpid(rdev_p->rscp);
243 		for (i = qpid+1; i & rdev_p->qpmask; i++) {
258 put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
272 cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
279 		if (!(pos->qpid & rdev_p->qpmask))
280 			cxio_hal_put_qpid(rdev_p->rscp, pos->qpid);
287 cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
294 cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
300 	wq->qpid = get_qpid(rdev_p, uctx);
308 	wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
323 	wq->doorbell = rdev_p->rnic_info.kdb_addr;
325 		wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
326 					(wq->qpid << rdev_p->qpshift);
327 	wq->rdev = rdev_p;
334 	cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
338 	put_qpid(rdev_p, wq->qpid, uctx);
343 cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
346 	err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
349 	dma_free_coherent(&(rdev_p->rnic_info.pdev),
357 	cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
362 cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
367 	dma_free_coherent(&(rdev_p->rnic_info.pdev),
376 	cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
378 	put_qpid(rdev_p, wq->qpid, uctx);
538 cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
541 	return (cxio_rdma_cq_setup(rdev_p, 0, 0, 1, 1, 0, 0));
545 cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
558 	err = cxio_hal_init_ctrl_cq(rdev_p);
564 	rdev_p->ctrl_qp.workq = contigmalloc((1 << T3_CTRL_QP_SIZE_LOG2)
566 	if (rdev_p->ctrl_qp.workq)
567 		rdev_p->ctrl_qp.dma_addr = vtophys(rdev_p->ctrl_qp.workq);
574 	rdev_p->ctrl_qp.doorbell = rdev_p->rnic_info.kdb_addr;
575 	memset(rdev_p->ctrl_qp.workq, 0,
578 	mtx_init(&rdev_p->ctrl_qp.lock, "ctl-qp lock", NULL, MTX_DEF|MTX_DUPOK);
581 	base_addr = rdev_p->ctrl_qp.dma_addr;
602 	     (unsigned long long) rdev_p->ctrl_qp.dma_addr,
603 	     rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
604 	return t3_offload_tx(rdev_p->adap, m);
611 cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
615 	dma_free_coherent(&(rdev_p->rnic_info.pdev),
617 			  * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
618 	    /* pci_unmap_addr(&rdev_p->ctrl_qp, mapping)*/ 0);
620 	contigfree(rdev_p->ctrl_qp.workq,(1UL << T3_CTRL_QP_SIZE_LOG2)
623 	return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
631 cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
643 	     rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
647 		if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
651 			     rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
652 			if (cxio_wait(&rdev_p->ctrl_qp,
653 				&rdev_p->ctrl_qp.lock,
654 				!Q_FULL(rdev_p->ctrl_qp.rptr,
655 					rdev_p->ctrl_qp.wptr,
664 		wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
706 		wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
710 		((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
717 			       Q_GENBIT(rdev_p->ctrl_qp.wptr,
721 			ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
724 		rdev_p->ctrl_qp.wptr++;
734 __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
749 		stag_idx = cxio_hal_get_stag(rdev_p->rscp);
757 	mtx_lock(&rdev_p->ctrl_qp.lock);
773 				    htobe32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
781 	err = cxio_hal_ctrl_qp_write_mem(rdev_p,
783 				       (rdev_p->rnic_info.tpt_base >> 5),
788 		cxio_hal_put_stag(rdev_p->rscp, stag_idx);
790 	wptr = rdev_p->ctrl_qp.wptr;
791 	mtx_unlock(&rdev_p->ctrl_qp.lock);
793 		if (cxio_wait(&rdev_p->ctrl_qp,
794 			&rdev_p->ctrl_qp.lock,
795 			SEQ32_GE(rdev_p->ctrl_qp.rptr, wptr)))
800 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
807 		__func__, pbl_addr, rdev_p->rnic_info.pbl_base,
810 	mtx_lock(&rdev_p->ctrl_qp.lock);
811 	err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
813 	wptr = rdev_p->ctrl_qp.wptr;
814 	mtx_unlock(&rdev_p->ctrl_qp.lock);
818 	if (cxio_wait(&rdev_p->ctrl_qp,
819                         &rdev_p->ctrl_qp.lock,
820                         SEQ32_GE(rdev_p->ctrl_qp.rptr, wptr)))
827 cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
832 	return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
837 cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
841 	return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
846 cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
849 	return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
854 cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
857 	return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
862 cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
864 	return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
869 cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr,
883 	CTR2(KTR_IW_CXGB, "%s rdev_p %p", __FUNCTION__, rdev_p);
892 	wqe->rq_addr = htobe32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
918 	rc = t3_offload_tx(rdev_p->adap, m);
929 	struct cxio_rdev *rdev_p = &rnicp->rdev;
947 		mtx_lock(&rdev_p->ctrl_qp.lock);
948 		rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
949 		wakeup(&rdev_p->ctrl_qp);
950 		mtx_unlock(&rdev_p->ctrl_qp.lock);
964 cxio_rdev_open(struct cxio_rdev *rdev_p)
967 	struct rdma_info *ri = &rdev_p->rnic_info;
968 	struct adapter *sc = rdev_p->adap;
970 	KASSERT(rdev_p->adap, ("%s: adap is NULL", __func__));
972 	memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
989 	cxio_init_ucontext(rdev_p, &rdev_p->uctx);
990 	rdev_p->qpshift = PAGE_SHIFT -
992 			            ilog2(rdev_p->rnic_info.udbell_len >>
994 	rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
995 	rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
997 	     rdev_p->adap, rdev_p->rnic_info.tpt_base,
998 	     rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p));
1000 	     rdev_p->rnic_info.pbl_base,
1001 	     rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
1002 	     rdev_p->rnic_info.rqt_top);
1005 	     rdev_p->rnic_info.udbell_len,
1006 	     rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
1007 	     rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
1009 	err = cxio_hal_init_ctrl_qp(rdev_p);
1015 	err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1023 	err = cxio_hal_pblpool_create(rdev_p);
1029 	err = cxio_hal_rqtpool_create(rdev_p);
1037 	cxio_hal_pblpool_destroy(rdev_p);
1039 	cxio_hal_destroy_resource(rdev_p->rscp);
1041 	cxio_hal_destroy_ctrl_qp(rdev_p);
1047 cxio_rdev_close(struct cxio_rdev *rdev_p)
1049 	cxio_hal_pblpool_destroy(rdev_p);
1050 	cxio_hal_rqtpool_destroy(rdev_p);
1051 	cxio_hal_destroy_ctrl_qp(rdev_p);
1052 	cxio_hal_destroy_resource(rdev_p->rscp);