Lines Matching defs:rate
151 #define MD1_CLK_1 0 /* 1/1 clock rate */
152 #define MD1_CLK_16 1 /* 1/16 clock rate */
153 #define MD1_CLK_32 2 /* 1/32 clock rate */
154 #define MD1_CLK_64 3 /* 1/64 clock rate */
165 unsigned clk : 2; /* clock rate */
180 #define MD2_DPLL_CLK_8 0 /* x8 ADPLL clock rate */
181 #define MD2_DPLL_CLK_16 1 /* x16 ADPLL clock rate */
182 #define MD2_DPLL_CLK_32 2 /* x32 ADPLL clock rate */
193 unsigned dpll_clk : 2; /* ADPLL clock rate */
256 unsigned long rate; /* data rate 2048/1024/512/256/128/64 kbit/s */
288 #define CLK_INT 0x40 /* internal baud rate generator */
370 unsigned long baud; /* data rate */