dev/bxe/bxe_elink.c

2731 	uint32_t wb_data[2];
2742 	wb_data[0] = val;
2743 	wb_data[1] = 0;
2744 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2752 	wb_data[0] = val;
2753 	wb_data[1] = 0;
2754 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2764 	uint32_t wb_data[2];
2775 	wb_data[0] = val;
2776 	wb_data[1] = 0;
2777 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2786 	wb_data[0] = val;
2787 	wb_data[1] = 0;
2788 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2793 		wb_data[0] = 0x0;
2794 		wb_data[0] |= (1<<0);  /* RX */
2795 		wb_data[0] |= (1<<1);  /* TX */
2796 		wb_data[0] |= (1<<2);  /* Force initial Xon */
2797 		wb_data[0] |= (1<<3);  /* 8 cos */
2798 		wb_data[0] |= (1<<5);  /* STATS */
2799 		wb_data[1] = 0;
2801 			    wb_data, 2);
2803 		wb_data[0] &= ~(1<<2);
2807 		wb_data[0] = 0x8;
2808 		wb_data[1] = 0;
2811 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2822 	wb_data[0] = val;
2823 	wb_data[1] = 0;
2825 		    wb_data, 2);
2837 	wb_data[0] = val;
2838 	wb_data[1] = 0;
2839 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3068 	uint32_t wb_data[2];
3074 	wb_data[0] = 0x3c;
3075 	wb_data[1] = 0;
3077 		    wb_data, 2);
3080 	wb_data[0] = ((params->mac_addr[2] << 24) |
3084 	wb_data[1] = ((params->mac_addr[0] << 8) |
3086 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3094 	wb_data[0] = val;
3095 	wb_data[1] = 0;
3096 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3099 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3100 	wb_data[1] = 0;
3101 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3106 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3107 	wb_data[1] = 0;
3108 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3111 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3112 	wb_data[1] = 0;
3113 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3116 	wb_data[0] = 0x1000200;
3117 	wb_data[1] = 0;
3119 		    wb_data, 2);
3123 		wb_data[0] = 0xf000;
3124 		wb_data[1] = 0;
3126 			    wb_data, 2);
3141 	uint32_t wb_data[2];
3145 	wb_data[0] = 0;
3146 	wb_data[1] = 0;
3147 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3151 	wb_data[0] = 0x3c;
3152 	wb_data[1] = 0;
3154 		    wb_data, 2);
3159 	wb_data[0] = ((params->mac_addr[2] << 24) |
3163 	wb_data[1] = ((params->mac_addr[0] << 8) |
3166 		    wb_data, 2);
3171 	wb_data[0] = 0x1000200;
3172 	wb_data[1] = 0;
3174 		    wb_data, 2);
3178 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3179 	wb_data[1] = 0;
3180 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3184 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3185 	wb_data[1] = 0;
3186 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3189 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3190 	wb_data[1] = 0;
3191 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3247 	uint32_t wb_data[2];
3259 		REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3261 			wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3263 			wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3264 		REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
14461 		uint32_t wb_data[2];
14470 		REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14471 		lss_status = (wb_data[0] > 0);