dev/bwi/if_bwi.c

770 	val = CSR_READ_4(sc, BWI_ID_HI);
805 		info = CSR_READ_4(sc, BWI_INFO);
810 		sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
938 		val = CSR_READ_4(sc, BWI_FLAGS);
995 			CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
997 			CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1084 		val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1097 		val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1145 	clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1268 			if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1271 			CSR_READ_4(sc, BWI_TXSTATUS1);
1527 		CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1576 	intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1584 	intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1605 		CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1668 			if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
2723 	val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2754 		status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2811 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2827 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
3314 	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3440 		tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3443 		tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3494 	val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3545 	busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3563 	val = CSR_READ_4(sc, BWI_STATE_LO);
3584 	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3608 		state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3621 		state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3641 	CSR_READ_4(sc, BWI_STATE_LO);
3650 	CSR_READ_4(sc, BWI_STATE_LO);
3669 	CSR_READ_4(sc, BWI_STATE_LO);
3672 	state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3676 	imstate = CSR_READ_4(sc, BWI_IMSTATE);
3689 	CSR_READ_4(sc, BWI_STATE_LO);
3698 	CSR_READ_4(sc, BWI_STATE_LO);