dev/bce/if_bce.c

377     struct cpu_reg *, struct fw_info *);
378 static void bce_start_cpu			(struct bce_softc *, struct cpu_reg *);
379 static void bce_halt_cpu			(struct bce_softc *, struct cpu_reg *);
4049 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4056     bce_halt_cpu(sc, cpu_reg);
4059 	offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4069 	offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4079 	offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4089 	offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4099 	offset = cpu_reg->spad_base +
4100 		(fw->rodata_addr - cpu_reg->mips_view_base);
4110 	REG_WR_IND(sc, cpu_reg->inst, 0);
4111 	REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4126 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4133 	val = REG_RD_IND(sc, cpu_reg->mode);
4134 	val &= ~cpu_reg->mode_value_halt;
4135 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4136 	REG_WR_IND(sc, cpu_reg->mode, val);
4149 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4156 	val = REG_RD_IND(sc, cpu_reg->mode);
4157 	val |= cpu_reg->mode_value_halt;
4158 	REG_WR_IND(sc, cpu_reg->mode, val);
4159 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4174 	struct cpu_reg cpu_reg;
4178 	cpu_reg.mode = BCE_RXP_CPU_MODE;
4179 	cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4180 	cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4181 	cpu_reg.state = BCE_RXP_CPU_STATE;
4182 	cpu_reg.state_value_clear = 0xffffff;
4183 	cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4184 	cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4185 	cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4186 	cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4187 	cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4188 	cpu_reg.spad_base = BCE_RXP_SCRATCH;
4189 	cpu_reg.mips_view_base = 0x8000000;
4192 	bce_start_cpu(sc, &cpu_reg);
4207 	struct cpu_reg cpu_reg;
4212 	cpu_reg.mode = BCE_RXP_CPU_MODE;
4213 	cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4214 	cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4215 	cpu_reg.state = BCE_RXP_CPU_STATE;
4216 	cpu_reg.state_value_clear = 0xffffff;
4217 	cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4218 	cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4219 	cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4220 	cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4221 	cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4222 	cpu_reg.spad_base = BCE_RXP_SCRATCH;
4223 	cpu_reg.mips_view_base = 0x8000000;
4288 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4305 	struct cpu_reg cpu_reg;
4310 	cpu_reg.mode = BCE_TXP_CPU_MODE;
4311 	cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4312 	cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4313 	cpu_reg.state = BCE_TXP_CPU_STATE;
4314 	cpu_reg.state_value_clear = 0xffffff;
4315 	cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4316 	cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4317 	cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4318 	cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4319 	cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4320 	cpu_reg.spad_base = BCE_TXP_SCRATCH;
4321 	cpu_reg.mips_view_base = 0x8000000;
4386 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4387     bce_start_cpu(sc, &cpu_reg);
4402 	struct cpu_reg cpu_reg;
4407 	cpu_reg.mode = BCE_TPAT_CPU_MODE;
4408 	cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4409 	cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4410 	cpu_reg.state = BCE_TPAT_CPU_STATE;
4411 	cpu_reg.state_value_clear = 0xffffff;
4412 	cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4413 	cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4414 	cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4415 	cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4416 	cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4417 	cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4418 	cpu_reg.mips_view_base = 0x8000000;
4483 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4484 	bce_start_cpu(sc, &cpu_reg);
4499 	struct cpu_reg cpu_reg;
4504 	cpu_reg.mode = BCE_CP_CPU_MODE;
4505 	cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4506 	cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4507 	cpu_reg.state = BCE_CP_CPU_STATE;
4508 	cpu_reg.state_value_clear = 0xffffff;
4509 	cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4510 	cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4511 	cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4512 	cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4513 	cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4514 	cpu_reg.spad_base = BCE_CP_SCRATCH;
4515 	cpu_reg.mips_view_base = 0x8000000;
4580 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4581 	bce_start_cpu(sc, &cpu_reg);
4596 	struct cpu_reg cpu_reg;
4601 	cpu_reg.mode = BCE_COM_CPU_MODE;
4602 	cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4603 	cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4604 	cpu_reg.state = BCE_COM_CPU_STATE;
4605 	cpu_reg.state_value_clear = 0xffffff;
4606 	cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4607 	cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4608 	cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4609 	cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4610 	cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4611 	cpu_reg.spad_base = BCE_COM_SCRATCH;
4612 	cpu_reg.mips_view_base = 0x8000000;
4677 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4678 	bce_start_cpu(sc, &cpu_reg);