Lines Matching refs:CVMX_ADD_IO_SEG
59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
114 return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
117 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
125 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
128 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
136 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
139 #define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
147 return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
150 #define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
158 return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
161 #define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
169 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
172 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
180 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
183 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
195 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
207 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
219 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
231 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
239 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
242 #define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
250 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
253 #define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
261 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
264 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
272 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
275 #define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
277 #define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
284 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
287 #define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
289 #define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
290 #define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
291 #define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
292 #define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
299 return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
302 #define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
310 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
313 #define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
321 return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
324 #define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
332 return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
335 #define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
343 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
346 #define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
354 return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
357 #define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
365 return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
368 #define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
376 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
379 #define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
387 return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
390 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
398 return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
401 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
409 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
412 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
424 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
432 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
435 #define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
443 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
446 #define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
454 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
457 #define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
465 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
468 #define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
476 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
479 #define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
487 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
490 #define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
498 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
501 #define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
509 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
512 #define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
520 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
523 #define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
531 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
534 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
542 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
545 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
553 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
556 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
564 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
567 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
575 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
578 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
586 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
589 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
597 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
600 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
608 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
611 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
619 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
622 #define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
630 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
633 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
641 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
644 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
652 return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
655 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
663 return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
666 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
674 return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
677 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
689 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
701 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
713 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
725 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
737 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
749 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
761 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
773 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
785 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
793 return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
796 #define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
804 return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
807 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
815 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
818 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
826 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
829 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
837 return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
840 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
848 return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
851 #define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
859 return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
862 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
870 return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
873 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
881 return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
884 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
892 return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
895 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
903 return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
906 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
914 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
917 #define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
929 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
937 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
940 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
948 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
951 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
959 return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
962 #define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
970 return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
973 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
981 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
984 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
992 return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
995 #define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
1003 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
1006 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
1014 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
1017 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
1025 return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
1028 #define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
1036 return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
1039 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
1047 return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
1050 #define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
1058 return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
1061 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
1069 return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
1072 #define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
1080 return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
1083 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
1091 return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
1094 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
1102 return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
1105 #define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
1113 return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
1116 #define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
1124 return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
1127 #define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
1135 return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
1138 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
1146 return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
1149 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
1157 return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
1160 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
1172 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16;
1175 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
1183 return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
1186 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
1194 return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
1197 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
1205 return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
1208 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
1216 return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
1219 #define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
1231 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
1234 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
1246 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
1249 #define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
1261 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
1264 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
1272 return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
1275 #define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
1287 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
1290 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
1298 return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
1301 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
1309 return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
1312 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
1320 return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
1323 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
1331 return CVMX_ADD_IO_SEG(0x00011F00000106C0ull);
1334 #define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
1342 return CVMX_ADD_IO_SEG(0x00011F00000106D0ull);
1345 #define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
1353 return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
1356 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
1364 return CVMX_ADD_IO_SEG(0x00011F0000013E10ull);
1367 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
1375 return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
1378 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
1390 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
1393 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
1401 return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
1404 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
1412 return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
1415 #define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
1423 return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
1426 #define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
1434 return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
1437 #define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
1445 return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
1448 #define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
1456 return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
1459 #define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
1467 return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
1470 #define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
1478 return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
1481 #define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
1489 return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
1492 #define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
1500 return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
1503 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
1511 return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
1514 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
1522 return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
1525 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
1533 return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
1536 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
1544 return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
1547 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
1555 return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
1558 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
1566 return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
1569 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
1577 return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
1580 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
1588 return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
1591 #define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
1599 return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
1602 #define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
1610 return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
1613 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
1621 return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
1624 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
1632 return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
1635 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
1647 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
1650 #define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
1662 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
1665 #define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
1677 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
1680 #define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
1692 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
1695 #define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
1707 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
1710 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
1721 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
1724 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
1736 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
1739 #define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
1751 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
1754 #define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
1766 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
1769 #define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
1781 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
1784 #define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
1792 return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
1795 #define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
1803 return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
1806 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
1814 return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
1817 #define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
1825 return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
1828 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
1836 return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
1839 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
1847 return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
1850 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
1858 return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
1861 #define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
1869 return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
1872 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
1880 return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
1883 #define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
1891 return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
1894 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
1902 return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
1905 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
1913 return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
1916 #define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
1924 return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
1927 #define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
1939 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
1942 #define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
1950 return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
1953 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
1961 return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
1964 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
1972 return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
1975 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
1983 return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
1986 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
1994 return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
1997 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
2005 return CVMX_ADD_IO_SEG(0x00011F0000011240ull);
2008 #define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
2016 return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
2019 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
2027 return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
2030 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
2038 return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
2041 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
2049 return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
2052 #define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
2060 return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
2063 #define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
2071 return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
2074 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
2082 return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
2085 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
2093 return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
2096 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
2104 return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16;
2107 #define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
2119 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16;
2122 #define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
2130 return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
2133 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
2141 return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
2144 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
2152 return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
2155 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
2163 return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
2166 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
2174 return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
2177 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
2185 return CVMX_ADD_IO_SEG(0x00011F0000011230ull);
2188 #define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
2196 return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
2199 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))