Lines Matching refs:chip
103 ** parameter page of the ONFI flash chip. */
152 * Array indexed by bootbus chip select with information
390 /* Internal helper function to set chip configuration to use default values */
391 static void __set_chip_defaults(int chip, int clocks_us)
395 cvmx_nand_state[chip].page_size = cvmx_nand_default.page_size; /* NAND page size in bytes */
396 cvmx_nand_state[chip].oob_size = cvmx_nand_default.oob_size; /* NAND OOB (spare) size in bytes (per page) */
397 cvmx_nand_state[chip].pages_per_block = cvmx_nand_default.pages_per_block;
398 cvmx_nand_state[chip].blocks = cvmx_nand_default.blocks;
399 cvmx_nand_state[chip].onfi_timing = cvmx_nand_default.onfi_timing;
400 __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
406 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
407 cvmx_nand_state[chip].blocks, cvmx_nand_state[chip].onfi_timing);
413 static int __wait_for_busy_done(int chip)
418 CVMX_NAND_LOG_PARAM("%d", chip);
460 * Each bit in this parameter represents a chip select that might
461 * contain NAND flash. Any chip select present in this bitmask may
463 * let the API probe all 8 chip selects.
469 int chip;
529 only chip select 1 is connected to NAND */
551 for (chip=start_chip; chip<stop_chip; chip++)
553 /* Skip chip selects that the caller didn't supply in the active chip bits */
554 if (((1<<chip) & active_chips) == 0)
556 __set_chip_defaults(chip, clocks_us);
563 for (chip=start_chip; chip<stop_chip; chip++)
570 /* Skip chip selects that the caller didn't supply in the active chip bits */
571 if (((1<<chip) & active_chips) == 0)
574 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(chip));
580 cvmx_nand_state[chip].page_size = 0;
581 cvmx_nand_state[chip].oob_size = 64;
582 cvmx_nand_state[chip].pages_per_block = 64;
583 cvmx_nand_state[chip].blocks = 100;
587 __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, 0);
592 cvmx_nand_state[chip].clen[0] = 0; /* Command doesn't need to be held before WE */
593 cvmx_nand_state[chip].clen[1] = 1; /* Twp, WE# pulse width */
594 cvmx_nand_state[chip].clen[2] = 3; /* Tclh, CLE hold time */
595 cvmx_nand_state[chip].clen[3] = 1;
597 cvmx_nand_state[chip].alen[0] = 4; /* Tals, ALE setup time */
598 cvmx_nand_state[chip].alen[1] = 1; /* Twp, WE# pulse width */
599 cvmx_nand_state[chip].alen[2] = 2; /* Twh, WE# pulse width high */
600 cvmx_nand_state[chip].alen[3] = 5; /* Talh, ALE hold time */
602 cvmx_nand_state[chip].rdn[0] = 0;
603 cvmx_nand_state[chip].rdn[1] = 6; /* Trp, RE# pulse width*/
604 cvmx_nand_state[chip].rdn[2] = 7; /* Treh, RE# high hold time */
605 cvmx_nand_state[chip].rdn[3] = 0;
607 cvmx_nand_state[chip].wrn[0] = 1; /* Twp, WE# pulse width */
608 cvmx_nand_state[chip].wrn[1] = 2; /* Twh, WE# pulse width high */
621 cvmx_nand_state[chip].flags |= CVMX_NAND_STATE_16BIT;
623 if (cvmx_nand_read_id(chip, 0x0, cvmx_ptr_to_phys(cvmx_nand_buffer), 16) < 16)
626 cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
633 cvmx_dprintf("%s: Probe returned nothing for chip %d\n", __FUNCTION__, chip);
637 /* Neither 8 or 16 bit mode worked, so go on to next chip select */
645 cvmx_dprintf("%s: NAND chip %d has ID 0x%08llx\n", __FUNCTION__, chip, (unsigned long long int)*(uint64_t*)cvmx_nand_buffer);
647 if (cvmx_nand_read_id(chip, 0x20, cvmx_ptr_to_phys(cvmx_nand_buffer), 8) < 8)
650 cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
659 cvmx_nand_read_param_page(chip, cvmx_ptr_to_phys(cvmx_nand_buffer), 2048);
664 ** from the parameter page that we need to access the chip. */
665 cvmx_nand_state[chip].page_size = cvmx_le32_to_cpu(onfi_param_page->page_data_bytes);
666 cvmx_nand_state[chip].oob_size = cvmx_le16_to_cpu(onfi_param_page->page_spare_bytes);
667 cvmx_nand_state[chip].pages_per_block = cvmx_le32_to_cpu(onfi_param_page->pages_per_block);
668 cvmx_nand_state[chip].blocks = cvmx_le32_to_cpu(onfi_param_page->blocks_per_lun) * onfi_param_page->number_lun;
680 cvmx_nand_state[chip].onfi_timing = mode;
684 cvmx_dprintf("%s: Invalid timing mode (%d) in ONFI parameter page, ignoring\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
685 cvmx_nand_state[chip].onfi_timing = 0;
689 cvmx_dprintf("%s: Using ONFI timing mode: %d\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
690 __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
691 if (cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size > CVMX_NAND_MAX_PAGE_AND_OOB_SIZE)
694 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, CVMX_NAND_MAX_PAGE_AND_OOB_SIZE);
697 /* We have completed setup for this ONFI chip, so go on to next chip. */
714 cvmx_dprintf("%s: Chip %d doesn't support ONFI.\n", __FUNCTION__, chip);
721 cvmx_nand_state[chip].page_size = 1024 << (nand_id_buffer[3] & 0x3); /* NAND page size in bytes */
723 cvmx_nand_state[chip].oob_size = (cvmx_nand_state[chip].page_size / 512) * ((nand_id_buffer[3] & 4) ? 16 : 8);
724 cvmx_nand_state[chip].pages_per_block = (0x10000 << ((nand_id_buffer[3] & 0x30) >> 4))/cvmx_nand_state[chip].page_size;
728 cvmx_nand_state[chip].oob_size = cvmx_nand_state[chip].page_size/64;
730 cvmx_nand_state[chip].oob_size *= 2;
732 cvmx_nand_state[chip].blocks = nand_size_bits/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
736 cvmx_nand_state[chip].onfi_timing = 6;
739 cvmx_nand_state[chip].onfi_timing = 2;
745 cvmx_dprintf("%s: Samsung NAND chip detected, using parameters decoded from ID bytes.\n", __FUNCTION__);
747 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
748 (int)(nand_size_bits/(8*1024*1024)), cvmx_nand_state[chip].onfi_timing);
751 __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
752 if (cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size > CVMX_NAND_MAX_PAGE_AND_OOB_SIZE)
755 __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, CVMX_NAND_MAX_PAGE_AND_OOB_SIZE);
759 /* We have completed setup for this Samsung chip, so go on to next chip. */
769 /* We were not able to automatically identify the NAND chip parameters. If default values were configured,
773 __set_chip_defaults(chip, clocks_us);
804 * Returns a bitmask representing the chip selects that are
807 * found. Each bit in the response coresponds to a chip select.
810 * each chip select (1<<chip).
814 int chip;
816 for (chip=0; chip<8; chip++)
818 if (cvmx_nand_state[chip].page_size)
819 result |= 1<<chip;
829 * Override the timing parameters for a NAND chip
831 * @param chip Chip select to override
841 cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[8], int clen[4], int alen[4], int rdn[4], int wrn[2])
846 if ((chip < 0) || (chip > 7))
848 if (!cvmx_nand_state[chip].page_size)
851 cvmx_nand_state[chip].tim_mult = tim_mult;
853 cvmx_nand_state[chip].tim_par[i] = tim_par[i];
855 cvmx_nand_state[chip].clen[i] = clen[i];
857 cvmx_nand_state[chip].alen[i] = alen[i];
859 cvmx_nand_state[chip].rdn[i] = rdn[i];
861 cvmx_nand_state[chip].wrn[i] = wrn[i];
949 * @param chip NAND chip to get data for
953 static inline int __cvmx_nand_get_column_bits(int chip)
955 return cvmx_pop(cvmx_nand_state[chip].page_size - 1);
964 * @param chip NAND chip to get data for
968 static inline int __cvmx_nand_get_row_bits(int chip)
970 return cvmx_pop(cvmx_nand_state[chip].blocks-1) + cvmx_pop(cvmx_nand_state[chip].pages_per_block-1);
979 * @param chip NAND chip to get data for
983 static inline int __cvmx_nand_get_address_cycles(int chip)
985 int address_bits = ((__cvmx_nand_get_column_bits(chip) + 7) >> 3) << 3;
986 address_bits += ((__cvmx_nand_get_row_bits(chip) + 7) >> 3) << 3;
994 * @param chip NAND chip to program
1007 static inline cvmx_nand_status_t __cvmx_nand_build_pre_cmd(int chip, int cmd_data, int num_address_cycles, uint64_t nand_address, int cmd_data2)
1017 cmd.set_tm_par.tim_mult = cvmx_nand_state[chip].tim_mult;
1019 cmd.set_tm_par.tim_par1 = cvmx_nand_state[chip].tim_par[1];
1020 cmd.set_tm_par.tim_par2 = cvmx_nand_state[chip].tim_par[2];
1021 cmd.set_tm_par.tim_par3 = cvmx_nand_state[chip].tim_par[3];
1022 cmd.set_tm_par.tim_par4 = cvmx_nand_state[chip].tim_par[4];
1023 cmd.set_tm_par.tim_par5 = cvmx_nand_state[chip].tim_par[5];
1024 cmd.set_tm_par.tim_par6 = cvmx_nand_state[chip].tim_par[6];
1025 cmd.set_tm_par.tim_par7 = cvmx_nand_state[chip].tim_par[7];
1038 /* Send chip select */
1040 cmd.chip_en.chip = chip;
1043 cmd.chip_en.width = (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT) ? 2 : 1;
1049 ** This meets chip enable to command latch enable timing.
1062 cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1063 cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1064 cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1075 if (num_address_cycles < __cvmx_nand_get_address_cycles(chip))
1082 int column_bits = __cvmx_nand_get_column_bits(chip);
1084 int column = nand_address & (cvmx_nand_state[chip].page_size-1);
1089 cmd.ale.alen1 = cvmx_nand_state[chip].alen[0];
1090 cmd.ale.alen2 = cvmx_nand_state[chip].alen[1];
1091 cmd.ale.alen3 = cvmx_nand_state[chip].alen[2];
1092 cmd.ale.alen4 = cvmx_nand_state[chip].alen[3];
1104 cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1105 cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1106 cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1129 /* Send chip deselect */
1153 * @param chip Chip select for NAND flash
1160 static inline void __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length)
1164 CVMX_NAND_LOG_PARAM("%d", chip);
1214 * @param chip Chip to read from
1230 static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length)
1237 CVMX_NAND_LOG_PARAM("%d", chip);
1245 if ((chip < 0) || (chip > 7))
1257 if (__cvmx_nand_build_pre_cmd(chip, nand_command1, address_cycles, nand_address, nand_command2))
1262 if (__wait_for_busy_done(chip))
1279 if (cvmx_nand_state[chip].onfi_timing >= 4)
1283 cmd.rd.rdn1 = cvmx_nand_state[chip].rdn[0];
1284 cmd.rd.rdn2 = cvmx_nand_state[chip].rdn[1];
1285 cmd.rd.rdn3 = cvmx_nand_state[chip].rdn[2];
1286 cmd.rd.rdn4 = cvmx_nand_state[chip].rdn[3];
1290 __cvmx_nand_setup_dma(chip, 0, buffer_address, buffer_length);
1316 * @param chip Chip select for NAND flash
1326 int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1331 CVMX_NAND_LOG_PARAM("%d", chip);
1336 if ((chip < 0) || (chip > 7))
1338 if (!cvmx_nand_state[chip].page_size)
1350 if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
1351 nand_address = (nand_address & ~(cvmx_nand_state[chip].page_size - 1)) | ((nand_address & (cvmx_nand_state[chip].page_size - 1)) >> 1);
1353 bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ, __cvmx_nand_get_address_cycles(chip), nand_address, NAND_COMMAND_READ_FIN, buffer_address, buffer_length);
1365 * @param chip Chip select for NAND flash
1373 cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address)
1379 CVMX_NAND_LOG_PARAM("%d", chip);
1383 if ((chip < 0) || (chip > 7))
1385 if (!cvmx_nand_state[chip].page_size)
1393 if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
1394 nand_address = (nand_address & ~(cvmx_nand_state[chip].page_size - 1)) | ((nand_address & (cvmx_nand_state[chip].page_size - 1)) >> 1);
1396 buffer_length = cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size;
1399 ** to a multiple of 8, otherwise we will transfer too much data to the NAND chip.
1406 if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_PROGRAM, __cvmx_nand_get_address_cycles(chip), nand_address, 0))
1413 cmd.wr.wrn1 = cvmx_nand_state[chip].wrn[0];
1414 cmd.wr.wrn2 = cvmx_nand_state[chip].wrn[1];
1421 cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1422 cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1423 cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1428 __cvmx_nand_setup_dma(chip, 1, buffer_address, buffer_length);
1431 if (__wait_for_busy_done(chip))
1454 * @param chip Chip select for NAND flash
1460 cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
1463 CVMX_NAND_LOG_PARAM("%d", chip);
1466 if ((chip < 0) || (chip > 7))
1468 if (!cvmx_nand_state[chip].page_size)
1472 if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_ERASE,
1473 (__cvmx_nand_get_row_bits(chip)+7) >> 3,
1474 nand_address >> __cvmx_nand_get_column_bits(chip),
1479 if (__wait_for_busy_done(chip))
1515 * @param chip Chip select for NAND flash
1526 int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1531 CVMX_NAND_LOG_PARAM("%d", chip);
1536 if ((chip < 0) || (chip > 7))
1545 bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_ID, 1, nand_address, 0, buffer_address, buffer_length);
1546 if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
1559 * @param chip Chip select for NAND flash
1567 int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length)
1572 CVMX_NAND_LOG_PARAM("%d", chip);
1576 if ((chip < 0) || (chip > 7))
1587 bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_PARAM_PAGE, 1, 0x0, 0, buffer_address, buffer_length);
1588 if (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT)
1597 * @param chip Chip select for NAND flash
1601 int cvmx_nand_get_status(int chip)
1604 int offset = !!(cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT); /* Normalize flag to 0/1 */
1607 CVMX_NAND_LOG_PARAM("%d", chip);
1609 if ((chip < 0) || (chip > 7))
1613 status = __cvmx_nand_low_level_read(chip, NAND_COMMAND_STATUS, 0, 0, 0, cvmx_ptr_to_phys(cvmx_nand_buffer), 8);
1626 * will return zero for chip selects not connected to NAND.
1628 * @param chip Chip select for NAND flash
1632 int cvmx_nand_get_page_size(int chip)
1635 CVMX_NAND_LOG_PARAM("%d", chip);
1637 if ((chip < 0) || (chip > 7))
1640 CVMX_NAND_RETURN(cvmx_nand_state[chip].page_size);
1647 * @param chip Chip select for NAND flash
1651 int cvmx_nand_get_oob_size(int chip)
1654 CVMX_NAND_LOG_PARAM("%d", chip);
1656 if ((chip < 0) || (chip > 7))
1659 CVMX_NAND_RETURN(cvmx_nand_state[chip].oob_size);
1666 * @param chip Chip select for NAND flash
1671 int cvmx_nand_get_pages_per_block(int chip)
1674 CVMX_NAND_LOG_PARAM("%d", chip);
1676 if ((chip < 0) || (chip > 7))
1679 CVMX_NAND_RETURN(cvmx_nand_state[chip].pages_per_block);
1686 * @param chip Chip select for NAND flash
1690 int cvmx_nand_get_blocks(int chip)
1693 CVMX_NAND_LOG_PARAM("%d", chip);
1695 if ((chip < 0) || (chip > 7))
1698 CVMX_NAND_RETURN(cvmx_nand_state[chip].blocks);
1705 * @param chip Chip select for NAND flash
1709 cvmx_nand_status_t cvmx_nand_reset(int chip)
1712 CVMX_NAND_LOG_PARAM("%d", chip);
1714 if ((chip < 0) || (chip > 7))
1716 if (!cvmx_nand_state[chip].page_size)
1719 if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_RESET, 0, 0, 0))
1723 if (__wait_for_busy_done(chip))