contrib/octeon-sdk/cvmx-nand.c

1157  * @param buffer_length
1160 static inline void __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length)
1167     CVMX_NAND_LOG_PARAM("%d", buffer_length);
1172     ndf_dma_cfg.s.size = ((buffer_length + 7) >> 3) - 1;
1185  * @param buffer_length
1188 static void __cvmx_nand_hex_dump(uint64_t buffer_address, int buffer_length)
1192     while (offset < buffer_length)
1200             if (offset+i < buffer_length)
1225  * @param buffer_length
1230 static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length)
1243     CVMX_NAND_LOG_PARAM("%d", buffer_length);
1251     if (buffer_length & 7)
1253     if (!buffer_length)
1278     cmd.rd.data_bytes = buffer_length;
1290     __cvmx_nand_setup_dma(chip, 0, buffer_address, buffer_length);
1321  * @param buffer_length
1326 int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1334     CVMX_NAND_LOG_PARAM("%d", buffer_length);
1344     if (buffer_length & 7)
1346     if (!buffer_length)
1353     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ, __cvmx_nand_get_address_cycles(chip), nand_address, NAND_COMMAND_READ_FIN, buffer_address, buffer_length);
1376     int buffer_length;
1396     buffer_length = cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size;
1403     buffer_length &= ~0x7;
1411     cmd.wr.data_bytes = buffer_length;
1428     __cvmx_nand_setup_dma(chip, 1, buffer_address, buffer_length);
1504 static void __cvmx_nand_fixup_16bit_id_reads(uint8_t *buf, int buffer_length)
1508     for (i = 0; i < buffer_length/2; i++)
1520  * @param buffer_length
1526 int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
1534     CVMX_NAND_LOG_PARAM("%d", buffer_length);
1542     if (!buffer_length)
1545     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_ID, 1, nand_address, 0, buffer_address, buffer_length);
1547         __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);
1562  * @param buffer_length
1567 int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length)
1574     CVMX_NAND_LOG_PARAM("%d", buffer_length);
1582     if (buffer_length & 7)
1584     if (!buffer_length)
1587     bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_PARAM_PAGE, 1, 0x0, 0, buffer_address, buffer_length);
1589         __cvmx_nand_fixup_16bit_id_reads(cvmx_phys_to_ptr(buffer_address), buffer_length);