Lines Matching refs:uint64_t
57 static inline uint64_t CVMX_EOI_BIST_CTL_STA_FUNC(void)
68 static inline uint64_t CVMX_EOI_CTL_STA_FUNC(void)
79 static inline uint64_t CVMX_EOI_DEF_STA0_FUNC(void)
90 static inline uint64_t CVMX_EOI_DEF_STA1_FUNC(void)
101 static inline uint64_t CVMX_EOI_DEF_STA2_FUNC(void)
112 static inline uint64_t CVMX_EOI_ECC_CTL_FUNC(void)
123 static inline uint64_t CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC(void)
134 static inline uint64_t CVMX_EOI_ENDOR_CLK_CTL_FUNC(void)
145 static inline uint64_t CVMX_EOI_ENDOR_CTL_FUNC(void)
156 static inline uint64_t CVMX_EOI_INT_ENA_FUNC(void)
167 static inline uint64_t CVMX_EOI_INT_STA_FUNC(void)
178 static inline uint64_t CVMX_EOI_IO_DRV_FUNC(void)
189 static inline uint64_t CVMX_EOI_THROTTLE_CTL_FUNC(void)
208 uint64_t u64;
211 uint64_t reserved_18_63 : 46;
212 uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */
213 uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1
215 uint64_t reserved_3_15 : 13;
216 uint64_t stdf : 1; /**< STDF Bist Status. */
217 uint64_t ppaf : 1; /**< PPAF Bist Status. */
218 uint64_t lddf : 1; /**< LDDF Bist Status. */
220 uint64_t lddf : 1;
221 uint64_t ppaf : 1;
222 uint64_t stdf : 1;
223 uint64_t reserved_3_15 : 13;
224 uint64_t start_bist : 1;
225 uint64_t clear_bist : 1;
226 uint64_t reserved_18_63 : 46;
240 uint64_t u64;
243 uint64_t reserved_13_63 : 51;
244 uint64_t ppaf_wm : 5; /**< Number of entries when PP Access FIFO will assert
246 uint64_t reserved_5_7 : 3;
247 uint64_t busy : 1; /**< 1: EOI is busy; 0: EOI is idle */
248 uint64_t rwam : 2; /**< Rread Write Aribitration Mode:
252 uint64_t ena : 1; /**< When reset, all the inbound DMA accesses will be
256 uint64_t reset : 1; /**< EOI block Software Reset. */
258 uint64_t reset : 1;
259 uint64_t ena : 1;
260 uint64_t rwam : 2;
261 uint64_t busy : 1;
262 uint64_t reserved_5_7 : 3;
263 uint64_t ppaf_wm : 5;
264 uint64_t reserved_13_63 : 51;
330 uint64_t u64;
333 uint64_t reserved_54_63 : 10;
334 uint64_t rout2 : 18; /**< Repairout2 */
335 uint64_t rout1 : 18; /**< Repairout1 */
336 uint64_t rout0 : 18; /**< Repairout0 */
338 uint64_t rout0 : 18;
339 uint64_t rout1 : 18;
340 uint64_t rout2 : 18;
341 uint64_t reserved_54_63 : 10;
356 uint64_t u64;
359 uint64_t reserved_54_63 : 10;
360 uint64_t rout5 : 18; /**< Repairout5 */
361 uint64_t rout4 : 18; /**< Repairout4 */
362 uint64_t rout3 : 18; /**< Repairout3 */
364 uint64_t rout3 : 18;
365 uint64_t rout4 : 18;
366 uint64_t rout5 : 18;
367 uint64_t reserved_54_63 : 10;
382 uint64_t u64;
385 uint64_t reserved_25_63 : 39;
386 uint64_t toomany : 1; /**< Toomanydefects */
387 uint64_t reserved_18_23 : 6;
388 uint64_t rout6 : 18; /**< Repairout6 */
390 uint64_t rout6 : 18;
391 uint64_t reserved_18_23 : 6;
392 uint64_t toomany : 1;
393 uint64_t reserved_25_63 : 39;
410 uint64_t u64;
413 uint64_t reserved_3_63 : 61;
414 uint64_t rben : 1; /**< 1: ECC Enable for read buffer
416 uint64_t rbsf : 2; /**< read buffer ecc syndrome flip
421 uint64_t rbsf : 2;
422 uint64_t rben : 1;
423 uint64_t reserved_3_63 : 61;
439 uint64_t u64;
442 uint64_t reserved_10_63 : 54;
443 uint64_t bisr_done : 1; /**< Endor DSP Memroy Bisr Done Status: 1 - done;
445 uint64_t failed : 1; /**< Bist/Bisr Status: 1 - failed; 0 - Not failed. */
446 uint64_t reserved_3_7 : 5;
447 uint64_t bisr_hr : 1; /**< BISR Hardrepair */
448 uint64_t bisr_dir : 1; /**< BISR Direction: 0 = input repair packets;
450 uint64_t start_bist : 1; /**< Start Bist */
452 uint64_t start_bist : 1;
453 uint64_t bisr_dir : 1;
454 uint64_t bisr_hr : 1;
455 uint64_t reserved_3_7 : 5;
456 uint64_t failed : 1;
457 uint64_t bisr_done : 1;
458 uint64_t reserved_10_63 : 54;
473 uint64_t u64;
476 uint64_t reserved_28_63 : 36;
477 uint64_t habclk_sel : 1; /**< HAB CLK select
480 uint64_t reserved_26_26 : 1;
481 uint64_t dsp_div_reset : 1; /**< DSP postscalar divider reset */
482 uint64_t dsp_ps_en : 3; /**< DSP postscalar divide ratio
493 uint64_t hab_div_reset : 1; /**< HAB postscalar divider reset */
494 uint64_t hab_ps_en : 3; /**< HAB postscalar divide ratio
505 uint64_t diffamp : 4; /**< PLL diffamp input transconductance */
506 uint64_t cps : 3; /**< PLL charge-pump current */
507 uint64_t cpb : 3; /**< PLL charge-pump current */
508 uint64_t reset_n : 1; /**< PLL reset */
509 uint64_t clkf : 7; /**< Multiply reference by CLKF
514 uint64_t clkf : 7;
515 uint64_t reset_n : 1;
516 uint64_t cpb : 3;
517 uint64_t cps : 3;
518 uint64_t diffamp : 4;
519 uint64_t hab_ps_en : 3;
520 uint64_t hab_div_reset : 1;
521 uint64_t dsp_ps_en : 3;
522 uint64_t dsp_div_reset : 1;
523 uint64_t reserved_26_26 : 1;
524 uint64_t habclk_sel : 1;
525 uint64_t reserved_28_63 : 36;
539 uint64_t u64;
542 uint64_t reserved_12_63 : 52;
543 uint64_t r_emod : 2; /**< Endian format for data read from the L2C.
549 uint64_t w_emod : 2; /**< Endian format for data written the L2C.
555 uint64_t inv_rsl_ra2 : 1; /**< Invert RSL CSR read address bit 2. */
556 uint64_t inv_rsl_wa2 : 1; /**< Invert RSL CSR write address bit 2. */
557 uint64_t inv_pp_ra2 : 1; /**< Invert PP CSR read address bit 2. */
558 uint64_t inv_pp_wa2 : 1; /**< Invert PP CSR write address bit 2. */
559 uint64_t reserved_1_3 : 3;
560 uint64_t reset : 1; /**< Endor block software reset. After hardware reset,
564 uint64_t reset : 1;
565 uint64_t reserved_1_3 : 3;
566 uint64_t inv_pp_wa2 : 1;
567 uint64_t inv_pp_ra2 : 1;
568 uint64_t inv_rsl_wa2 : 1;
569 uint64_t inv_rsl_ra2 : 1;
570 uint64_t w_emod : 2;
571 uint64_t r_emod : 2;
572 uint64_t reserved_12_63 : 52;
587 uint64_t u64;
590 uint64_t reserved_2_63 : 62;
591 uint64_t rb_dbe : 1; /**< Read Buffer ECC DBE */
592 uint64_t rb_sbe : 1; /**< Read Buffer ECC SBE */
594 uint64_t rb_sbe : 1;
595 uint64_t rb_dbe : 1;
596 uint64_t reserved_2_63 : 62;
611 uint64_t u64;
614 uint64_t reserved_2_63 : 62;
615 uint64_t rb_dbe : 1; /**< Read Buffer ECC DBE */
616 uint64_t rb_sbe : 1; /**< Read Buffer ECC SBE */
618 uint64_t rb_sbe : 1;
619 uint64_t rb_dbe : 1;
620 uint64_t reserved_2_63 : 62;
635 uint64_t u64;
638 uint64_t reserved_24_63 : 40;
639 uint64_t rfif_p : 6; /**< RFIF output driver P-Mos control */
640 uint64_t rfif_n : 6; /**< RFIF output driver N-Mos control */
641 uint64_t gpo_p : 6; /**< GPO output driver P-Mos control */
642 uint64_t gpo_n : 6; /**< GPO output driver N-Mos control */
644 uint64_t gpo_n : 6;
645 uint64_t gpo_p : 6;
646 uint64_t rfif_n : 6;
647 uint64_t rfif_p : 6;
648 uint64_t reserved_24_63 : 40;
662 uint64_t u64;
665 uint64_t reserved_21_63 : 43;
666 uint64_t std : 5; /**< Number of outstanding store data accepted by EOI on
669 uint64_t reserved_10_15 : 6;
670 uint64_t stc : 2; /**< Number of outstanding L2C store command accepted by
673 uint64_t reserved_4_7 : 4;
674 uint64_t ldc : 4; /**< Number of outstanding L2C loads. The value must be
677 uint64_t ldc : 4;
678 uint64_t reserved_4_7 : 4;
679 uint64_t stc : 2;
680 uint64_t reserved_10_15 : 6;
681 uint64_t std : 5;
682 uint64_t reserved_21_63 : 43;