contrib/octeon-sdk/cvmx-endor-defs.h

61 	return CVMX_ADD_IO_SEG(0x00010F0000844004ull);
64 #define CVMX_ENDOR_ADMA_AUTO_CLK_GATE (CVMX_ADD_IO_SEG(0x00010F0000844004ull))
72 	return CVMX_ADD_IO_SEG(0x00010F0000844044ull);
75 #define CVMX_ENDOR_ADMA_AXIERR_INTR (CVMX_ADD_IO_SEG(0x00010F0000844044ull))
83 	return CVMX_ADD_IO_SEG(0x00010F0000844050ull);
86 #define CVMX_ENDOR_ADMA_AXI_RSPCODE (CVMX_ADD_IO_SEG(0x00010F0000844050ull))
94 	return CVMX_ADD_IO_SEG(0x00010F0000844084ull);
97 #define CVMX_ENDOR_ADMA_AXI_SIGNAL (CVMX_ADD_IO_SEG(0x00010F0000844084ull))
105 	return CVMX_ADD_IO_SEG(0x00010F0000844040ull);
108 #define CVMX_ENDOR_ADMA_DMADONE_INTR (CVMX_ADD_IO_SEG(0x00010F0000844040ull))
116 	return CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16;
119 #define CVMX_ENDOR_ADMA_DMAX_ADDR_HI(offset) (CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16)
127 	return CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16;
130 #define CVMX_ENDOR_ADMA_DMAX_ADDR_LO(offset) (CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16)
138 	return CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16;
141 #define CVMX_ENDOR_ADMA_DMAX_CFG(offset) (CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16)
149 	return CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16;
152 #define CVMX_ENDOR_ADMA_DMAX_SIZE(offset) (CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16)
160 	return CVMX_ADD_IO_SEG(0x00010F0000844080ull);
163 #define CVMX_ENDOR_ADMA_DMA_PRIORITY (CVMX_ADD_IO_SEG(0x00010F0000844080ull))
171 	return CVMX_ADD_IO_SEG(0x00010F0000844008ull);
174 #define CVMX_ENDOR_ADMA_DMA_RESET (CVMX_ADD_IO_SEG(0x00010F0000844008ull))
182 	return CVMX_ADD_IO_SEG(0x00010F000084404Cull);
185 #define CVMX_ENDOR_ADMA_INTR_DIS (CVMX_ADD_IO_SEG(0x00010F000084404Cull))
193 	return CVMX_ADD_IO_SEG(0x00010F0000844048ull);
196 #define CVMX_ENDOR_ADMA_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F0000844048ull))
204 	return CVMX_ADD_IO_SEG(0x00010F0000844000ull);
207 #define CVMX_ENDOR_ADMA_MODULE_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844000ull))
215 	return CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8;
218 #define CVMX_ENDOR_INTC_CNTL_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8)
226 	return CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8;
229 #define CVMX_ENDOR_INTC_CNTL_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8)
237 	return CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8;
240 #define CVMX_ENDOR_INTC_INDEX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8)
248 	return CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8;
251 #define CVMX_ENDOR_INTC_INDEX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8)
259 	return CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64;
262 #define CVMX_ENDOR_INTC_MISC_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64)
270 	return CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64;
273 #define CVMX_ENDOR_INTC_MISC_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64)
281 	return CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64;
284 #define CVMX_ENDOR_INTC_MISC_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64)
292 	return CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64;
295 #define CVMX_ENDOR_INTC_MISC_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64)
303 	return CVMX_ADD_IO_SEG(0x00010F0000820194ull);
306 #define CVMX_ENDOR_INTC_MISC_RINT (CVMX_ADD_IO_SEG(0x00010F0000820194ull))
314 	return CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64;
317 #define CVMX_ENDOR_INTC_MISC_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64)
325 	return CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64;
328 #define CVMX_ENDOR_INTC_MISC_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64)
336 	return CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64;
339 #define CVMX_ENDOR_INTC_RDQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64)
347 	return CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64;
350 #define CVMX_ENDOR_INTC_RDQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64)
358 	return CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64;
361 #define CVMX_ENDOR_INTC_RDQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64)
369 	return CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64;
372 #define CVMX_ENDOR_INTC_RDQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64)
380 	return CVMX_ADD_IO_SEG(0x00010F000082018Cull);
383 #define CVMX_ENDOR_INTC_RDQ_RINT (CVMX_ADD_IO_SEG(0x00010F000082018Cull))
391 	return CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64;
394 #define CVMX_ENDOR_INTC_RDQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64)
402 	return CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64;
405 #define CVMX_ENDOR_INTC_RDQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64)
413 	return CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64;
416 #define CVMX_ENDOR_INTC_RD_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64)
424 	return CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64;
427 #define CVMX_ENDOR_INTC_RD_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64)
435 	return CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64;
438 #define CVMX_ENDOR_INTC_RD_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64)
446 	return CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64;
449 #define CVMX_ENDOR_INTC_RD_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64)
457 	return CVMX_ADD_IO_SEG(0x00010F0000820184ull);
460 #define CVMX_ENDOR_INTC_RD_RINT (CVMX_ADD_IO_SEG(0x00010F0000820184ull))
468 	return CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64;
471 #define CVMX_ENDOR_INTC_RD_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64)
479 	return CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64;
482 #define CVMX_ENDOR_INTC_RD_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64)
490 	return CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8;
493 #define CVMX_ENDOR_INTC_STAT_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8)
501 	return CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8;
504 #define CVMX_ENDOR_INTC_STAT_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8)
512 	return CVMX_ADD_IO_SEG(0x00010F0000820204ull);
515 #define CVMX_ENDOR_INTC_SWCLR (CVMX_ADD_IO_SEG(0x00010F0000820204ull))
523 	return CVMX_ADD_IO_SEG(0x00010F0000820200ull);
526 #define CVMX_ENDOR_INTC_SWSET (CVMX_ADD_IO_SEG(0x00010F0000820200ull))
534 	return CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64;
537 #define CVMX_ENDOR_INTC_SW_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64)
545 	return CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64;
548 #define CVMX_ENDOR_INTC_SW_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64)
556 	return CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64;
559 #define CVMX_ENDOR_INTC_SW_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64)
567 	return CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64;
570 #define CVMX_ENDOR_INTC_SW_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64)
578 	return CVMX_ADD_IO_SEG(0x00010F0000820190ull);
581 #define CVMX_ENDOR_INTC_SW_RINT (CVMX_ADD_IO_SEG(0x00010F0000820190ull))
589 	return CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64;
592 #define CVMX_ENDOR_INTC_SW_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64)
600 	return CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64;
603 #define CVMX_ENDOR_INTC_SW_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64)
611 	return CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64;
614 #define CVMX_ENDOR_INTC_WRQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64)
622 	return CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64;
625 #define CVMX_ENDOR_INTC_WRQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64)
633 	return CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64;
636 #define CVMX_ENDOR_INTC_WRQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64)
644 	return CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64;
647 #define CVMX_ENDOR_INTC_WRQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64)
655 	return CVMX_ADD_IO_SEG(0x00010F0000820188ull);
658 #define CVMX_ENDOR_INTC_WRQ_RINT (CVMX_ADD_IO_SEG(0x00010F0000820188ull))
666 	return CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64;
669 #define CVMX_ENDOR_INTC_WRQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64)
677 	return CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64;
680 #define CVMX_ENDOR_INTC_WRQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64)
688 	return CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64;
691 #define CVMX_ENDOR_INTC_WR_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64)
699 	return CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64;
702 #define CVMX_ENDOR_INTC_WR_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64)
710 	return CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64;
713 #define CVMX_ENDOR_INTC_WR_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64)
721 	return CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64;
724 #define CVMX_ENDOR_INTC_WR_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64)
732 	return CVMX_ADD_IO_SEG(0x00010F0000820180ull);
735 #define CVMX_ENDOR_INTC_WR_RINT (CVMX_ADD_IO_SEG(0x00010F0000820180ull))
743 	return CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64;
746 #define CVMX_ENDOR_INTC_WR_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64)
754 	return CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64;
757 #define CVMX_ENDOR_INTC_WR_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64)
765 	return CVMX_ADD_IO_SEG(0x00010F0000832054ull);
768 #define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832054ull))
776 	return CVMX_ADD_IO_SEG(0x00010F000083205Cull);
779 #define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 (CVMX_ADD_IO_SEG(0x00010F000083205Cull))
787 	return CVMX_ADD_IO_SEG(0x00010F0000832064ull);
790 #define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832064ull))
798 	return CVMX_ADD_IO_SEG(0x00010F000083206Cull);
801 #define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083206Cull))
809 	return CVMX_ADD_IO_SEG(0x00010F0000832050ull);
812 #define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832050ull))
820 	return CVMX_ADD_IO_SEG(0x00010F0000832058ull);
823 #define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832058ull))
831 	return CVMX_ADD_IO_SEG(0x00010F0000832060ull);
834 #define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832060ull))
842 	return CVMX_ADD_IO_SEG(0x00010F0000832068ull);
845 #define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F0000832068ull))
853 	return CVMX_ADD_IO_SEG(0x00010F0000832018ull);
856 #define CVMX_ENDOR_OFS_HMM_INTR_CLEAR (CVMX_ADD_IO_SEG(0x00010F0000832018ull))
864 	return CVMX_ADD_IO_SEG(0x00010F000083201Cull);
867 #define CVMX_ENDOR_OFS_HMM_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F000083201Cull))
875 	return CVMX_ADD_IO_SEG(0x00010F0000832014ull);
878 #define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS (CVMX_ADD_IO_SEG(0x00010F0000832014ull))
886 	return CVMX_ADD_IO_SEG(0x00010F0000832010ull);
889 #define CVMX_ENDOR_OFS_HMM_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832010ull))
897 	return CVMX_ADD_IO_SEG(0x00010F0000832020ull);
900 #define CVMX_ENDOR_OFS_HMM_INTR_TEST (CVMX_ADD_IO_SEG(0x00010F0000832020ull))
908 	return CVMX_ADD_IO_SEG(0x00010F0000832004ull);
911 #define CVMX_ENDOR_OFS_HMM_MODE (CVMX_ADD_IO_SEG(0x00010F0000832004ull))
919 	return CVMX_ADD_IO_SEG(0x00010F0000832030ull);
922 #define CVMX_ENDOR_OFS_HMM_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832030ull))
930 	return CVMX_ADD_IO_SEG(0x00010F0000832034ull);
933 #define CVMX_ENDOR_OFS_HMM_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832034ull))
941 	return CVMX_ADD_IO_SEG(0x00010F0000832038ull);
944 #define CVMX_ENDOR_OFS_HMM_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832038ull))
952 	return CVMX_ADD_IO_SEG(0x00010F000083203Cull);
955 #define CVMX_ENDOR_OFS_HMM_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083203Cull))
963 	return CVMX_ADD_IO_SEG(0x00010F0000832000ull);
966 #define CVMX_ENDOR_OFS_HMM_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832000ull))
974 	return CVMX_ADD_IO_SEG(0x00010F000083202Cull);
977 #define CVMX_ENDOR_OFS_HMM_XFER_CNT (CVMX_ADD_IO_SEG(0x00010F000083202Cull))
985 	return CVMX_ADD_IO_SEG(0x00010F000083200Cull);
988 #define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS (CVMX_ADD_IO_SEG(0x00010F000083200Cull))
996 	return CVMX_ADD_IO_SEG(0x00010F0000832028ull);
999 #define CVMX_ENDOR_OFS_HMM_XFER_START (CVMX_ADD_IO_SEG(0x00010F0000832028ull))
1007 	return CVMX_ADD_IO_SEG(0x00010F00008680CCull);
1010 #define CVMX_ENDOR_RFIF_1PPS_GEN_CFG (CVMX_ADD_IO_SEG(0x00010F00008680CCull))
1018 	return CVMX_ADD_IO_SEG(0x00010F0000868104ull);
1021 #define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET (CVMX_ADD_IO_SEG(0x00010F0000868104ull))
1029 	return CVMX_ADD_IO_SEG(0x00010F0000868110ull);
1032 #define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN (CVMX_ADD_IO_SEG(0x00010F0000868110ull))
1040 	return CVMX_ADD_IO_SEG(0x00010F0000868114ull);
1043 #define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868114ull))
1051 	return CVMX_ADD_IO_SEG(0x00010F0000868010ull);
1054 #define CVMX_ENDOR_RFIF_CONF (CVMX_ADD_IO_SEG(0x00010F0000868010ull))
1062 	return CVMX_ADD_IO_SEG(0x00010F000086801Cull);
1065 #define CVMX_ENDOR_RFIF_CONF2 (CVMX_ADD_IO_SEG(0x00010F000086801Cull))
1073 	return CVMX_ADD_IO_SEG(0x00010F00008684C0ull);
1076 #define CVMX_ENDOR_RFIF_DSP1_GPIO (CVMX_ADD_IO_SEG(0x00010F00008684C0ull))
1084 	return CVMX_ADD_IO_SEG(0x00010F000086840Cull);
1087 #define CVMX_ENDOR_RFIF_DSP_RX_HIS (CVMX_ADD_IO_SEG(0x00010F000086840Cull))
1095 	return CVMX_ADD_IO_SEG(0x00010F0000868400ull);
1098 #define CVMX_ENDOR_RFIF_DSP_RX_ISM (CVMX_ADD_IO_SEG(0x00010F0000868400ull))
1106 	return CVMX_ADD_IO_SEG(0x00010F00008684C4ull);
1109 #define CVMX_ENDOR_RFIF_FIRS_ENABLE (CVMX_ADD_IO_SEG(0x00010F00008684C4ull))
1117 	return CVMX_ADD_IO_SEG(0x00010F0000868030ull);
1120 #define CVMX_ENDOR_RFIF_FRAME_CNT (CVMX_ADD_IO_SEG(0x00010F0000868030ull))
1128 	return CVMX_ADD_IO_SEG(0x00010F0000868014ull);
1131 #define CVMX_ENDOR_RFIF_FRAME_L (CVMX_ADD_IO_SEG(0x00010F0000868014ull))
1139 	return CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4;
1142 #define CVMX_ENDOR_RFIF_GPIO_X(offset) (CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4)
1150 	return CVMX_ADD_IO_SEG(0x00010F00008680DCull);
1153 #define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680DCull))
1161 	return CVMX_ADD_IO_SEG(0x00010F00008680E0ull);
1164 #define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E0ull))
1172 	return CVMX_ADD_IO_SEG(0x00010F0000868018ull);
1175 #define CVMX_ENDOR_RFIF_NUM_RX_WIN (CVMX_ADD_IO_SEG(0x00010F0000868018ull))
1183 	return CVMX_ADD_IO_SEG(0x00010F0000868180ull);
1186 #define CVMX_ENDOR_RFIF_PWM_ENABLE (CVMX_ADD_IO_SEG(0x00010F0000868180ull))
1194 	return CVMX_ADD_IO_SEG(0x00010F0000868184ull);
1197 #define CVMX_ENDOR_RFIF_PWM_HIGH_TIME (CVMX_ADD_IO_SEG(0x00010F0000868184ull))
1205 	return CVMX_ADD_IO_SEG(0x00010F0000868188ull);
1208 #define CVMX_ENDOR_RFIF_PWM_LOW_TIME (CVMX_ADD_IO_SEG(0x00010F0000868188ull))
1216 	return CVMX_ADD_IO_SEG(0x00010F00008681ACull);
1219 #define CVMX_ENDOR_RFIF_RD_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681ACull))
1227 	return CVMX_ADD_IO_SEG(0x00010F00008681B0ull);
1230 #define CVMX_ENDOR_RFIF_RD_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681B0ull))
1238 	return CVMX_ADD_IO_SEG(0x00010F00008680C8ull);
1241 #define CVMX_ENDOR_RFIF_REAL_TIME_TIMER (CVMX_ADD_IO_SEG(0x00010F00008680C8ull))
1249 	return CVMX_ADD_IO_SEG(0x00010F0000868194ull);
1252 #define CVMX_ENDOR_RFIF_RF_CLK_TIMER (CVMX_ADD_IO_SEG(0x00010F0000868194ull))
1260 	return CVMX_ADD_IO_SEG(0x00010F0000868198ull);
1263 #define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN (CVMX_ADD_IO_SEG(0x00010F0000868198ull))
1271 	return CVMX_ADD_IO_SEG(0x00010F00008680E8ull);
1274 #define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E8ull))
1282 	return CVMX_ADD_IO_SEG(0x00010F0000868004ull);
1285 #define CVMX_ENDOR_RFIF_RX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868004ull))
1293 	return CVMX_ADD_IO_SEG(0x00010F0000868500ull);
1296 #define CVMX_ENDOR_RFIF_RX_FIFO_CNT (CVMX_ADD_IO_SEG(0x00010F0000868500ull))
1304 	return CVMX_ADD_IO_SEG(0x00010F0000868038ull);
1307 #define CVMX_ENDOR_RFIF_RX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868038ull))
1315 	return CVMX_ADD_IO_SEG(0x00010F0000868020ull);
1318 #define CVMX_ENDOR_RFIF_RX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868020ull))
1326 	return CVMX_ADD_IO_SEG(0x00010F0000868508ull);
1329 #define CVMX_ENDOR_RFIF_RX_LOAD_CFG (CVMX_ADD_IO_SEG(0x00010F0000868508ull))
1337 	return CVMX_ADD_IO_SEG(0x00010F00008680D4ull);
1340 #define CVMX_ENDOR_RFIF_RX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D4ull))
1348 	return CVMX_ADD_IO_SEG(0x00010F0000868108ull);
1351 #define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868108ull))
1359 	return CVMX_ADD_IO_SEG(0x00010F0000868000ull);
1362 #define CVMX_ENDOR_RFIF_RX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868000ull))
1370 	return CVMX_ADD_IO_SEG(0x00010F00008680C4ull);
1373 #define CVMX_ENDOR_RFIF_RX_SYNC_SCNT (CVMX_ADD_IO_SEG(0x00010F00008680C4ull))
1381 	return CVMX_ADD_IO_SEG(0x00010F00008680C0ull);
1384 #define CVMX_ENDOR_RFIF_RX_SYNC_VALUE (CVMX_ADD_IO_SEG(0x00010F00008680C0ull))
1392 	return CVMX_ADD_IO_SEG(0x00010F0000868410ull);
1395 #define CVMX_ENDOR_RFIF_RX_TH (CVMX_ADD_IO_SEG(0x00010F0000868410ull))
1403 	return CVMX_ADD_IO_SEG(0x00010F000086850Cull);
1406 #define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE (CVMX_ADD_IO_SEG(0x00010F000086850Cull))
1414 	return CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4;
1417 #define CVMX_ENDOR_RFIF_RX_W_EX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4)
1425 	return CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4;
1428 #define CVMX_ENDOR_RFIF_RX_W_SX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4)
1436 	return CVMX_ADD_IO_SEG(0x00010F00008680E4ull);
1439 #define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG (CVMX_ADD_IO_SEG(0x00010F00008680E4ull))
1447 	return CVMX_ADD_IO_SEG(0x00010F0000868100ull);
1450 #define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR (CVMX_ADD_IO_SEG(0x00010F0000868100ull))
1458 	return CVMX_ADD_IO_SEG(0x00010F0000868028ull);
1461 #define CVMX_ENDOR_RFIF_SAMPLE_CNT (CVMX_ADD_IO_SEG(0x00010F0000868028ull))
1469 	return CVMX_ADD_IO_SEG(0x00010F0000868444ull);
1472 #define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS (CVMX_ADD_IO_SEG(0x00010F0000868444ull))
1480 	return CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4;
1483 #define CVMX_ENDOR_RFIF_SPI_CMDSX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4)
1491 	return CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4;
1494 #define CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4)
1502 	return CVMX_ADD_IO_SEG(0x00010F0000868428ull);
1505 #define CVMX_ENDOR_RFIF_SPI_CONF0 (CVMX_ADD_IO_SEG(0x00010F0000868428ull))
1513 	return CVMX_ADD_IO_SEG(0x00010F000086842Cull);
1516 #define CVMX_ENDOR_RFIF_SPI_CONF1 (CVMX_ADD_IO_SEG(0x00010F000086842Cull))
1524 	return CVMX_ADD_IO_SEG(0x00010F0000866008ull);
1527 #define CVMX_ENDOR_RFIF_SPI_CTRL (CVMX_ADD_IO_SEG(0x00010F0000866008ull))
1535 	return CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4;
1538 #define CVMX_ENDOR_RFIF_SPI_DINX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4)
1546 	return CVMX_ADD_IO_SEG(0x00010F0000866000ull);
1549 #define CVMX_ENDOR_RFIF_SPI_RX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866000ull))
1557 	return CVMX_ADD_IO_SEG(0x00010F0000866010ull);
1560 #define CVMX_ENDOR_RFIF_SPI_STATUS (CVMX_ADD_IO_SEG(0x00010F0000866010ull))
1568 	return CVMX_ADD_IO_SEG(0x00010F0000866004ull);
1571 #define CVMX_ENDOR_RFIF_SPI_TX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866004ull))
1579 	return CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4;
1582 #define CVMX_ENDOR_RFIF_SPI_X_LL(offset) (CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4)
1590 	return CVMX_ADD_IO_SEG(0x00010F00008681A0ull);
1593 #define CVMX_ENDOR_RFIF_TIMER64_CFG (CVMX_ADD_IO_SEG(0x00010F00008681A0ull))
1601 	return CVMX_ADD_IO_SEG(0x00010F000086819Cull);
1604 #define CVMX_ENDOR_RFIF_TIMER64_EN (CVMX_ADD_IO_SEG(0x00010F000086819Cull))
1612 	return CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4;
1615 #define CVMX_ENDOR_RFIF_TTI_SCNT_INTX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4)
1623 	return CVMX_ADD_IO_SEG(0x00010F0000868118ull);
1626 #define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR (CVMX_ADD_IO_SEG(0x00010F0000868118ull))
1634 	return CVMX_ADD_IO_SEG(0x00010F0000868124ull);
1637 #define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN (CVMX_ADD_IO_SEG(0x00010F0000868124ull))
1645 	return CVMX_ADD_IO_SEG(0x00010F0000868120ull);
1648 #define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP (CVMX_ADD_IO_SEG(0x00010F0000868120ull))
1656 	return CVMX_ADD_IO_SEG(0x00010F000086811Cull);
1659 #define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT (CVMX_ADD_IO_SEG(0x00010F000086811Cull))
1667 	return CVMX_ADD_IO_SEG(0x00010F000086800Cull);
1670 #define CVMX_ENDOR_RFIF_TX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F000086800Cull))
1678 	return CVMX_ADD_IO_SEG(0x00010F0000868034ull);
1681 #define CVMX_ENDOR_RFIF_TX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868034ull))
1689 	return CVMX_ADD_IO_SEG(0x00010F0000868024ull);
1692 #define CVMX_ENDOR_RFIF_TX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868024ull))
1700 	return CVMX_ADD_IO_SEG(0x00010F00008680D8ull);
1703 #define CVMX_ENDOR_RFIF_TX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D8ull))
1711 	return CVMX_ADD_IO_SEG(0x00010F000086810Cull);
1714 #define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F000086810Cull))
1722 	return CVMX_ADD_IO_SEG(0x00010F0000868008ull);
1725 #define CVMX_ENDOR_RFIF_TX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868008ull))
1733 	return CVMX_ADD_IO_SEG(0x00010F0000868414ull);
1736 #define CVMX_ENDOR_RFIF_TX_TH (CVMX_ADD_IO_SEG(0x00010F0000868414ull))
1744 	return CVMX_ADD_IO_SEG(0x00010F0000868040ull);
1747 #define CVMX_ENDOR_RFIF_WIN_EN (CVMX_ADD_IO_SEG(0x00010F0000868040ull))
1755 	return CVMX_ADD_IO_SEG(0x00010F000086803Cull);
1758 #define CVMX_ENDOR_RFIF_WIN_UPD_SCNT (CVMX_ADD_IO_SEG(0x00010F000086803Cull))
1766 	return CVMX_ADD_IO_SEG(0x00010F00008681A4ull);
1769 #define CVMX_ENDOR_RFIF_WR_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681A4ull))
1777 	return CVMX_ADD_IO_SEG(0x00010F00008681A8ull);
1780 #define CVMX_ENDOR_RFIF_WR_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681A8ull))
1788 	return CVMX_ADD_IO_SEG(0x00010F0000844428ull);
1791 #define CVMX_ENDOR_RSTCLK_CLKENB0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844428ull))
1799 	return CVMX_ADD_IO_SEG(0x00010F0000844424ull);
1802 #define CVMX_ENDOR_RSTCLK_CLKENB0_SET (CVMX_ADD_IO_SEG(0x00010F0000844424ull))
1810 	return CVMX_ADD_IO_SEG(0x00010F0000844420ull);
1813 #define CVMX_ENDOR_RSTCLK_CLKENB0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844420ull))
1821 	return CVMX_ADD_IO_SEG(0x00010F0000844438ull);
1824 #define CVMX_ENDOR_RSTCLK_CLKENB1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844438ull))
1832 	return CVMX_ADD_IO_SEG(0x00010F0000844434ull);
1835 #define CVMX_ENDOR_RSTCLK_CLKENB1_SET (CVMX_ADD_IO_SEG(0x00010F0000844434ull))
1843 	return CVMX_ADD_IO_SEG(0x00010F0000844430ull);
1846 #define CVMX_ENDOR_RSTCLK_CLKENB1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844430ull))
1854 	return CVMX_ADD_IO_SEG(0x00010F0000844448ull);
1857 #define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR (CVMX_ADD_IO_SEG(0x00010F0000844448ull))
1865 	return CVMX_ADD_IO_SEG(0x00010F0000844444ull);
1868 #define CVMX_ENDOR_RSTCLK_DSPSTALL_SET (CVMX_ADD_IO_SEG(0x00010F0000844444ull))
1876 	return CVMX_ADD_IO_SEG(0x00010F0000844440ull);
1879 #define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE (CVMX_ADD_IO_SEG(0x00010F0000844440ull))
1887 	return CVMX_ADD_IO_SEG(0x00010F0000844598ull);
1890 #define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK (CVMX_ADD_IO_SEG(0x00010F0000844598ull))
1898 	return CVMX_ADD_IO_SEG(0x00010F0000844590ull);
1901 #define CVMX_ENDOR_RSTCLK_INTR0_MASK (CVMX_ADD_IO_SEG(0x00010F0000844590ull))
1909 	return CVMX_ADD_IO_SEG(0x00010F0000844594ull);
1912 #define CVMX_ENDOR_RSTCLK_INTR0_SETMASK (CVMX_ADD_IO_SEG(0x00010F0000844594ull))
1920 	return CVMX_ADD_IO_SEG(0x00010F000084459Cull);
1923 #define CVMX_ENDOR_RSTCLK_INTR0_STATUS (CVMX_ADD_IO_SEG(0x00010F000084459Cull))
1931 	return CVMX_ADD_IO_SEG(0x00010F00008445A8ull);
1934 #define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK (CVMX_ADD_IO_SEG(0x00010F00008445A8ull))
1942 	return CVMX_ADD_IO_SEG(0x00010F00008445A0ull);
1945 #define CVMX_ENDOR_RSTCLK_INTR1_MASK (CVMX_ADD_IO_SEG(0x00010F00008445A0ull))
1953 	return CVMX_ADD_IO_SEG(0x00010F00008445A4ull);
1956 #define CVMX_ENDOR_RSTCLK_INTR1_SETMASK (CVMX_ADD_IO_SEG(0x00010F00008445A4ull))
1964 	return CVMX_ADD_IO_SEG(0x00010F00008445ACull);
1967 #define CVMX_ENDOR_RSTCLK_INTR1_STATUS (CVMX_ADD_IO_SEG(0x00010F00008445ACull))
1975 	return CVMX_ADD_IO_SEG(0x00010F0000844450ull);
1978 #define CVMX_ENDOR_RSTCLK_PHY_CONFIG (CVMX_ADD_IO_SEG(0x00010F0000844450ull))
1986 	return CVMX_ADD_IO_SEG(0x00010F00008445B0ull);
1989 #define CVMX_ENDOR_RSTCLK_PROC_MON (CVMX_ADD_IO_SEG(0x00010F00008445B0ull))
1997 	return CVMX_ADD_IO_SEG(0x00010F00008445B4ull);
2000 #define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT (CVMX_ADD_IO_SEG(0x00010F00008445B4ull))
2008 	return CVMX_ADD_IO_SEG(0x00010F0000844408ull);
2011 #define CVMX_ENDOR_RSTCLK_RESET0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844408ull))
2019 	return CVMX_ADD_IO_SEG(0x00010F0000844404ull);
2022 #define CVMX_ENDOR_RSTCLK_RESET0_SET (CVMX_ADD_IO_SEG(0x00010F0000844404ull))
2030 	return CVMX_ADD_IO_SEG(0x00010F0000844400ull);
2033 #define CVMX_ENDOR_RSTCLK_RESET0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844400ull))
2041 	return CVMX_ADD_IO_SEG(0x00010F0000844418ull);
2044 #define CVMX_ENDOR_RSTCLK_RESET1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844418ull))
2052 	return CVMX_ADD_IO_SEG(0x00010F0000844414ull);
2055 #define CVMX_ENDOR_RSTCLK_RESET1_SET (CVMX_ADD_IO_SEG(0x00010F0000844414ull))
2063 	return CVMX_ADD_IO_SEG(0x00010F0000844410ull);
2066 #define CVMX_ENDOR_RSTCLK_RESET1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844410ull))
2074 	return CVMX_ADD_IO_SEG(0x00010F0000844588ull);
2077 #define CVMX_ENDOR_RSTCLK_SW_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844588ull))
2085 	return CVMX_ADD_IO_SEG(0x00010F0000844584ull);
2088 #define CVMX_ENDOR_RSTCLK_SW_INTR_SET (CVMX_ADD_IO_SEG(0x00010F0000844584ull))
2096 	return CVMX_ADD_IO_SEG(0x00010F0000844580ull);
2099 #define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844580ull))
2107 	return CVMX_ADD_IO_SEG(0x00010F0000844500ull);
2110 #define CVMX_ENDOR_RSTCLK_TIMER_CTL (CVMX_ADD_IO_SEG(0x00010F0000844500ull))
2118 	return CVMX_ADD_IO_SEG(0x00010F0000844534ull);
2121 #define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844534ull))
2129 	return CVMX_ADD_IO_SEG(0x00010F0000844530ull);
2132 #define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844530ull))
2140 	return CVMX_ADD_IO_SEG(0x00010F0000844508ull);
2143 #define CVMX_ENDOR_RSTCLK_TIMER_MAX (CVMX_ADD_IO_SEG(0x00010F0000844508ull))
2151 	return CVMX_ADD_IO_SEG(0x00010F0000844504ull);
2154 #define CVMX_ENDOR_RSTCLK_TIMER_VALUE (CVMX_ADD_IO_SEG(0x00010F0000844504ull))
2162 	return CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4;
2165 #define CVMX_ENDOR_RSTCLK_TIMEX_THRD(offset) (CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4)
2173 	return CVMX_ADD_IO_SEG(0x00010F0000844570ull);
2176 #define CVMX_ENDOR_RSTCLK_VERSION (CVMX_ADD_IO_SEG(0x00010F0000844570ull))