contrib/octeon-sdk/cvmx-dma-engine.c

144         cvmx_npei_dma_control_t dma_control;
145         dma_control.u64 = 0;
147             dma_control.s.dma4_enb = 1;
148         dma_control.s.dma3_enb = 1;
149         dma_control.s.dma2_enb = 1;
150         dma_control.s.dma1_enb = 1;
151         dma_control.s.dma0_enb = 1;
152         dma_control.s.o_mode = 1; /* Pull NS and RO from this register, not the pointers */
153         //dma_control.s.dwb_denb = 1;
154         //dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
155         dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
156         dma_control.s.csize = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
157         cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
175         cvmx_dpi_dma_control_t dma_control;
190         dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
191         dma_control.s.pkt_hp = 1;
192         dma_control.s.pkt_en = 1;
193         dma_control.s.dma_enb = 0x1f;
194         dma_control.s.dwb_denb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
195         dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
196         dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
197         dma_control.s.o_mode = 1;
198         cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
199         /* When dma_control[pkt_en] = 1, engine 5 is used for packets and is not
210         cvmx_npi_dma_control_t dma_control;
211         dma_control.u64 = 0;
212         //dma_control.s.dwb_denb = 1;
213         //dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
214         dma_control.s.o_add1 = 1;
215         dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
216         dma_control.s.hp_enb = 1;
217         dma_control.s.lp_enb = 1;
218         dma_control.s.csize = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
219         cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);
249         cvmx_npei_dma_control_t dma_control;
250         dma_control.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMA_CONTROL);
252             dma_control.s.dma4_enb = 0;
253         dma_control.s.dma3_enb = 0;
254         dma_control.s.dma2_enb = 0;
255         dma_control.s.dma1_enb = 0;
256         dma_control.s.dma0_enb = 0;
257         cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
263         cvmx_dpi_dma_control_t dma_control;
264         dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL);
265         dma_control.s.dma_enb = 0;
266         cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
272         cvmx_npi_dma_control_t dma_control;
273         dma_control.u64 = cvmx_read_csr(CVMX_NPI_DMA_CONTROL);
274         dma_control.s.hp_enb = 0;
275         dma_control.s.lp_enb = 0;
276         cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);