Lines Matching refs:series
693 HAL_11N_RATE_SERIES series[],
733 tx_mode = ar9300_get_tx_mode(series[0].RateFlags);
734 txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex,
735 series[0].ChSel, tx_mode);
741 set_11n_tx_power(0, AH_MIN(txpower, series[0].tx_power_cap));
747 ads->ds_ctl13 = set_11n_tries(series, 0)
748 | set_11n_tries(series, 1)
749 | set_11n_tries(series, 2)
750 | set_11n_tries(series, 3)
754 ads->ds_ctl14 = set_11n_rate(series, 0)
755 | set_11n_rate(series, 1)
756 | set_11n_rate(series, 2)
757 | set_11n_rate(series, 3);
759 ads->ds_ctl15 = set_11n_pkt_dur_rts_cts(series, 0)
760 | set_11n_pkt_dur_rts_cts(series, 1);
762 ads->ds_ctl16 = set_11n_pkt_dur_rts_cts(series, 2)
763 | set_11n_pkt_dur_rts_cts(series, 3);
765 ads->ds_ctl18 = set_11n_rate_flags(series, 0)
766 | set_11n_rate_flags(series, 1)
767 | set_11n_rate_flags(series, 2)
768 | set_11n_rate_flags(series, 3)
778 tx_mode = ar9300_get_tx_mode(series[1].RateFlags);
780 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode);
785 set_11n_tx_power(1, AH_MIN(txpower, series[1].tx_power_cap));
790 tx_mode = ar9300_get_tx_mode(series[2].RateFlags);
792 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode);
797 set_11n_tx_power(2, AH_MIN(txpower, series[2].tx_power_cap));
801 tx_mode = ar9300_get_tx_mode(series[3].RateFlags);
803 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode);
808 set_11n_tx_power(3, AH_MIN(txpower, series[3].tx_power_cap));
814 * ctl19 for rate series 0 ... ctrl22 for series 3