Lines Matching defs:ti_mmchs_read_4
170 * ti_mmchs_read_4 - reads a 32-bit value from a register
183 ti_mmchs_read_4(struct ti_mmchs_softc *sc, bus_size_t off)
212 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
221 while (!(ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0))
226 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0))
229 if (ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit)
296 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD);
348 cmd->resp[3] = ti_mmchs_read_4(sc, MMCHS_RSP10);
349 cmd->resp[2] = ti_mmchs_read_4(sc, MMCHS_RSP32);
350 cmd->resp[1] = ti_mmchs_read_4(sc, MMCHS_RSP54);
351 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP76);
353 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP10);
359 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD);
394 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DE) {
397 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DDIR)
453 stat_reg = ti_mmchs_read_4(sc, MMCHS_STAT) & (ti_mmchs_read_4(sc,
588 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
893 ie = ti_mmchs_read_4(sc, MMCHS_IE);
897 ise = ti_mmchs_read_4(sc, MMCHS_ISE);
901 con = ti_mmchs_read_4(sc, MMCHS_CON);
916 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC));
932 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC));
940 ti_mmchs_read_4(sc, MMCHS_STAT);
982 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
983 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
1010 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
1037 while (!(ti_mmchs_read_4(sc, MMCHS_HCTL) & MMCHS_HCTL_SDBP)) {
1045 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
1065 sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
1097 while (((sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL)) &
1111 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
1347 sysconfig = ti_mmchs_read_4(sc, MMCHS_SYSCONFIG);
1351 while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 0x01) == 0x0) {
1360 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
1363 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & MMCHS_SYSCTL_SRA) != 0x0) {
1374 capa = ti_mmchs_read_4(sc, MMCHS_CAPA);
1389 con = ti_mmchs_read_4(sc, MMCHS_CON) & MMCHS_CON_DVAL_MASK;