Lines Matching refs:sel_val
164 uint32_t sel_val;
176 .sel_val = 0,
200 .sel_val = 0,
212 .sel_val = 0x3, /* Divided PLL4 main clock */
224 .sel_val = CKO1_PLL4_DIVD,
236 .sel_val = 0,
248 .sel_val = 0,
260 .sel_val = 0,
272 .sel_val = 0,
284 .sel_val = 0,
296 .sel_val = 0,
316 .sel_val = 0x3, /* Divided PLL4 main clock */
381 reg |= (clk->sel_val << clk->sel_shift);