Lines Matching defs:reg_value
116 uint32_t reg_value = 0;
196 reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
197 reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
198 reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
199 reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
200 reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
201 A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
204 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
205 reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
206 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
229 uint32_t reg_value = 0;
266 reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
267 reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
268 A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
271 reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
272 reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
273 reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
274 reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
275 reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
276 A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);