Lines Matching defs:reg_value
127 uint32_t reg_value;
133 reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
134 reg_value |= CCM_AHB_GATING_USB0; /* AHB clock gate usb0 */
135 reg_value |= CCM_AHB_GATING_EHCI0; /* AHB clock gate ehci1 */
136 reg_value |= CCM_AHB_GATING_EHCI1; /* AHB clock gate ehci1 */
137 ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
140 reg_value = ccm_read_4(sc, CCM_USB_CLK);
141 reg_value |= CCM_USB_PHY; /* USBPHY */
142 reg_value |= CCM_USB0_RESET; /* disable reset for USB0 */
143 reg_value |= CCM_USB1_RESET; /* disable reset for USB1 */
144 reg_value |= CCM_USB2_RESET; /* disable reset for USB2 */
145 ccm_write_4(sc, CCM_USB_CLK, reg_value);
154 uint32_t reg_value;
160 reg_value = ccm_read_4(sc, CCM_USB_CLK);
161 reg_value &= ~CCM_USB_PHY; /* USBPHY */
162 reg_value &= ~CCM_USB0_RESET; /* reset for USB0 */
163 reg_value &= ~CCM_USB1_RESET; /* reset for USB1 */
164 reg_value &= ~CCM_USB2_RESET; /* reset for USB2 */
165 ccm_write_4(sc, CCM_USB_CLK, reg_value);
168 reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
169 reg_value &= ~CCM_AHB_GATING_USB0; /* disable AHB clock gate usb0 */
170 reg_value &= ~CCM_AHB_GATING_EHCI1; /* disable AHB clock gate ehci1 */
171 ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
179 uint32_t reg_value;
185 reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
186 reg_value |= CCM_AHB_GATING_EMAC;
187 ccm_write_4(sc, CCM_AHB_GATING0, reg_value);