Lines Matching defs:Cond
193 SmallVectorImpl<MachineOperand> &Cond,
226 Cond.push_back(MachineOperand::CreateImm(BranchCode));
227 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(MachineOperand::CreateImm(BranchCode));
249 Cond.push_back(SecondLastInst->getOperand(0));
281 const SmallVectorImpl<MachineOperand> &Cond,
285 assert((Cond.size() == 2 || Cond.size() == 0) &&
289 if (Cond.empty()) {
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
295 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 assert(Cond.size() == 2 && "Unexpected number of components!");
303 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
304 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
396 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
397 assert((Cond.size() == 2) &&
399 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));