Target/X86/X86ISelLowering.cpp

5032     SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5034     return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5051     SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5053     return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
6304   SDValue NewV;
6310     NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6313     NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6315     // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6341       V1 = NewV;
6352       NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6354       ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6357       V1 = NewV.getOperand(0);
6424     NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6427     if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6428       ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6429       NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6430                                   NewV.getOperand(0),
6448     NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6451     if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6452       ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6453       NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6454                                   NewV.getOperand(0),
6463     NewV = V1;
6481     NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6484   return NewV;
6554   SDValue NewV = V1;
6576       NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6612     NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6615   return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);