Lines Matching defs:TRI
86 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
90 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
94 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
116 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
133 const SIRegisterInfo *TRI,
143 RC = TRI->getSubRegClass(RC, SubReg);
148 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
159 const SIRegisterInfo *TRI,
164 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
165 return TRI->getSubRegClass(RC, SubReg);
169 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
172 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
177 const SIRegisterInfo *TRI,
190 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
191 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
196 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
207 if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
222 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
227 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
229 if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) {
233 if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
240 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
249 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
250 !hasVGPROperands(MI, TRI))