Target/R600/R600ISelLowering.cpp

35   addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
55   setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
56   setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
57   setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
58   setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
66   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
76   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
78   setOperationAction(ISD::SETCC, MVT::i32, Expand);
82   setOperationAction(ISD::SELECT, MVT::i32, Expand);
90   setOperationAction(ISD::LOAD, MVT::i32, Custom);
104   setOperationAction(ISD::STORE, MVT::i32, Custom);
107   setTruncStoreAction(MVT::i32, MVT::i8, Custom);
108   setTruncStoreAction(MVT::i32, MVT::i16, Custom);
110   setOperationAction(ISD::LOAD, MVT::i32, Custom);
112   setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
120   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
536         DAG.getConstant(0, MVT::i32), // SWZ_X
537         DAG.getConstant(1, MVT::i32), // SWZ_Y
538         DAG.getConstant(2, MVT::i32), // SWZ_Z
539         DAG.getConstant(3, MVT::i32) // SWZ_W
577             MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
595             MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
599             MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
612             MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
616             MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
672         DAG.getConstant(TextureOp, MVT::i32),
674         DAG.getConstant(0, MVT::i32),
675         DAG.getConstant(1, MVT::i32),
676         DAG.getConstant(2, MVT::i32),
677         DAG.getConstant(3, MVT::i32),
681         DAG.getConstant(0, MVT::i32),
682         DAG.getConstant(1, MVT::i32),
683         DAG.getConstant(2, MVT::i32),
684         DAG.getConstant(3, MVT::i32),
697           DAG.getConstant(0, MVT::i32)),
699           DAG.getConstant(0, MVT::i32)),
701           DAG.getConstant(1, MVT::i32)),
703           DAG.getConstant(1, MVT::i32)),
705           DAG.getConstant(2, MVT::i32)),
707           DAG.getConstant(2, MVT::i32)),
709           DAG.getConstant(3, MVT::i32)),
711           DAG.getConstant(3, MVT::i32))
836                      DAG.getConstant(ByteOffset, MVT::i32), // PTR
873   // select_cc i32, i32, -1,  0, cc_supported
879      ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
895       (CompareVT == VT || VT == MVT::i32)) {
905   // select_cc f32, 0.0, i32, i32, cc_supported
906   // select_cc i32, 0,   f32, f32, cc_supported
907   // select_cc i32, 0,   i32, i32, cc_supported
946       CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
975   } else if (CompareVT == MVT::i32) {
1016                      DAG.getConstant(SRLPad, MVT::i32));
1063       assert(VT.bitsLE(MVT::i32));
1067         MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1070         MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1073                                       DAG.getConstant(2, MVT::i32));
1081       // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1085         DAG.getConstant(0, MVT::i32),
1086         DAG.getConstant(0, MVT::i32),
1095                Value.getValueType().bitsGE(MVT::i32)) {
1099                                     Ptr, DAG.getConstant(2, MVT::i32)));
1136       Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1137                         DAG.getConstant(PtrIncr, MVT::i32));
1139                                  Value, DAG.getConstant(i, MVT::i32));
1143                               DAG.getTargetConstant(Channel, MVT::i32));
1148       Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1151     DAG.getTargetConstant(0, MVT::i32)); // Channel
1231             DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1232         Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1244           DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1246                           AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1251       Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1252           DAG.getConstant(0, MVT::i32));
1273           DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1309       Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1310                         DAG.getConstant(PtrIncr, MVT::i32));
1313                              DAG.getTargetConstant(Channel, MVT::i32),
1324                               DAG.getTargetConstant(0, MVT::i32), // Channel
1376                                  DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1387    if (!VT.isVector()) return MVT::i32;
1480       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1488       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1514   // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1515   // (i32 select_cc f32, f32, -1, 0 cc)
1536                            DAG.getConstant(-1, MVT::i32), // True
1537                            DAG.getConstant(0, MVT::i32),  // Flase
1725     Neg = DAG.getTargetConstant(1, MVT::i32);
1731     Abs = DAG.getTargetConstant(1, MVT::i32);
1828       Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
1830     Src = DAG.getRegister(ImmReg, MVT::i32);
1918     Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);