Target/PowerPC/PPCFastISel.cpp

147     bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
409     unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
411             ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
412     Addr.Base.Reg = ResultReg;
429 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
435   // If ResultReg is given, it determines the register class of the load.
443     (ResultReg ? MRI.getRegClass(ResultReg) :
488   if (ResultReg == 0)
489     ResultReg = createResultReg(UseRC);
502     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
508     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
532     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
562   unsigned ResultReg = 0;
563   if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
565   UpdateValueMap(I, ResultReg);
905   unsigned ResultReg = 0;
906   if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
909   return ResultReg;
1012   unsigned ResultReg = 0;
1013   if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1016   return ResultReg;
1116   unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1164         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1166         UpdateValueMap(I, ResultReg);
1180   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1182   UpdateValueMap(I, ResultReg);
1318     unsigned ResultReg = 0;
1322       ResultReg = createResultReg(CpyRC);
1325               TII.get(TargetOpcode::COPY), ResultReg)
1330       ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1332               ResultReg).addReg(SourcePhysReg);
1339       ResultReg = createResultReg(&PPC::GPRCRegClass);
1343               TII.get(TargetOpcode::COPY), ResultReg)
1347     assert(ResultReg && "ResultReg unset!");
1349     UpdateValueMap(I, ResultReg);
1692     unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1694             ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1695     SrcReg = ResultReg;
1732   unsigned ResultReg = createResultReg(RC);
1734   if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1737   UpdateValueMap(I, ResultReg);
1911   unsigned ResultReg = createResultReg(RC);
1916             TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1925             TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1930             TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1933   return ResultReg;
1983     unsigned ResultReg = createResultReg(RC);
1985             ResultReg).addReg(TmpReg3).addImm(Lo);
1986     return ResultReg;
2057     unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2059             ResultReg).addFrameIndex(SI->second).addImm(0);
2060     return ResultReg;
2070 // them.  Thus ResultReg should be the def reg for the last redundant
2135   unsigned ResultReg = MI->getOperand(0).getReg();
2137   if (!PPCEmitLoad(VT, ResultReg, Addr, 0, IsZExt))