Lines Matching defs:Cond
73 SmallVectorImpl<MachineOperand> &Cond) const {
80 Cond.push_back(MachineOperand::CreateImm(Opc));
83 Cond.push_back(Inst->getOperand(i));
89 SmallVectorImpl<MachineOperand> &Cond,
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99 const SmallVectorImpl<MachineOperand>& Cond)
101 unsigned Opc = Cond[0].getImm();
105 for (unsigned i = 1; i < Cond.size(); ++i) {
106 if (Cond[i].isReg())
107 MIB.addReg(Cond[i].getReg());
108 else if (Cond[i].isImm())
109 MIB.addImm(Cond[i].getImm());
119 const SmallVectorImpl<MachineOperand> &Cond,
129 assert((Cond.size() <= 3) &&
134 BuildCondBr(MBB, TBB, DL, Cond);
141 if (Cond.empty())
144 BuildCondBr(MBB, TBB, DL, Cond);
175 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
177 assert( (Cond.size() && Cond.size() <= 3) &&
179 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
185 MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond,
232 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
261 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);