Lines Matching refs:i32
109 if (ElemTy == MVT::i32) {
433 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
435 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
633 setIndexedLoadAction(im, MVT::i32, Legal);
637 setIndexedStoreAction(im, MVT::i32, Legal);
643 setOperationAction(ISD::MULHU, MVT::i32, Expand);
645 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
646 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
650 setOperationAction(ISD::MULHS, MVT::i32, Expand);
652 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
653 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
654 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
660 setOperationAction(ISD::ADDC, MVT::i32, Custom);
661 setOperationAction(ISD::ADDE, MVT::i32, Custom);
662 setOperationAction(ISD::SUBC, MVT::i32, Custom);
663 setOperationAction(ISD::SUBE, MVT::i32, Custom);
667 setOperationAction(ISD::ROTL, MVT::i32, Expand);
668 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
671 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
674 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
675 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
681 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
686 setOperationAction(ISD::SDIV, MVT::i32, Expand);
687 setOperationAction(ISD::UDIV, MVT::i32, Expand);
691 setOperationAction(ISD::SREM, MVT::i32, Expand);
692 setOperationAction(ISD::UREM, MVT::i32, Expand);
713 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
714 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
716 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
717 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
720 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
721 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
722 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
723 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
724 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
743 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
776 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
777 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
778 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
779 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
780 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
781 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
782 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
783 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
784 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
785 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
790 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
791 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
808 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
814 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
819 setOperationAction(ISD::SETCC, MVT::i32, Expand);
822 setOperationAction(ISD::SELECT, MVT::i32, Custom);
825 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
830 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
861 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
862 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
863 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
864 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
869 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
1333 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1342 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1347 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1356 DAG.getConstant(0, MVT::i32));
1359 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1363 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1368 DAG.getConstant(1, MVT::i32));
1415 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1523 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1527 DAG.getConstant(0, MVT::i32));
1529 DAG.getConstant(1, MVT::i32));
1549 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1550 assert(VA.getLocVT() == MVT::i32 &&
1552 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1574 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1599 MVT::i32);
1600 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1673 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1688 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1709 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1714 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1738 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1743 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2139 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2188 DAG.getConstant(0, MVT::i32));
2190 DAG.getVTList(MVT::i32, MVT::i32), Half);
2204 DAG.getConstant(1, MVT::i32));
2206 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2209 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
2340 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2373 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2391 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2397 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2442 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2448 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2460 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2502 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2527 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2575 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2583 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2608 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2612 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2619 SDValue Val = DAG.getConstant(0, MVT::i32);
2621 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2629 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2656 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2663 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2689 DAG.getConstant(0, MVT::i32));
2706 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2707 DAG.getConstant(Domain, MVT::i32));
2733 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2734 DAG.getConstant(isData, MVT::i32));
2766 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2775 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2780 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2911 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3029 else if (RegVT == MVT::i32)
3150 RHS = DAG.getConstant(C-1, MVT::i32);
3157 RHS = DAG.getConstant(C-1, MVT::i32);
3164 RHS = DAG.getConstant(C+1, MVT::i32);
3171 RHS = DAG.getConstant(C+1, MVT::i32);
3190 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3343 if (LHS.getValueType() == MVT::i32) {
3365 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3404 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3406 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3410 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3444 return DAG.getConstant(0, MVT::i32);
3447 return DAG.getLoad(MVT::i32, SDLoc(Op),
3458 RetVal1 = DAG.getConstant(0, MVT::i32);
3459 RetVal2 = DAG.getConstant(0, MVT::i32);
3465 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3475 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3510 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3513 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3515 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3527 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3528 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3530 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3547 if (LHS.getValueType() == MVT::i32) {
3550 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3568 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3570 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3575 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3593 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3605 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3624 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3657 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3664 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3730 DAG.getTargetConstant(EncodedVal, MVT::i32));
3735 DAG.getConstant(32, MVT::i32));
3743 DAG.getConstant(32, MVT::i32));
3747 DAG.getConstant(32, MVT::i32));
3752 MVT::i32);
3763 DAG.getConstant(0, MVT::i32));
3771 // Bitcast operand 1 to i32.
3773 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3775 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3778 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3779 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3780 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3782 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3783 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3785 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3789 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3792 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3793 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3807 SDValue Offset = DAG.getConstant(4, MVT::i32);
3814 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3854 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3855 DAG.getConstant(0, MVT::i32));
3856 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3857 DAG.getConstant(1, MVT::i32));
3865 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3882 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3889 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3904 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3905 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3907 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3908 DAG.getConstant(VTBits, MVT::i32));
3913 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3914 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3925 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3938 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3939 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3941 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3942 DAG.getConstant(VTBits, MVT::i32));
3947 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3948 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3965 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3967 MVT::i32));
3968 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3969 DAG.getConstant(1U << 22, MVT::i32));
3970 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3971 DAG.getConstant(22, MVT::i32));
3972 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3973 DAG.getConstant(3, MVT::i32));
4090 if (VT.getVectorElementType() == MVT::i32)
4110 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4127 DAG.getConstant(vshiftInt, MVT::i32),
4136 // We can get here for a node like i32 = ISD::SHL i32, i64
4152 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4153 DAG.getConstant(0, MVT::i32));
4154 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4155 DAG.getConstant(1, MVT::i32));
4160 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
4163 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4433 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4458 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4462 DAG.getConstant(0, MVT::i32));
4479 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4493 DAG.getConstant(0, MVT::i32));
4496 // Finally, try a VMVN.i32
4510 DAG.getConstant(0, MVT::i32));
4773 return DAG.getConstant(Val, MVT::i32);
4776 return DAG.getConstant(Val, MVT::i32);
4820 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4878 // i32 and try again.
4902 Value, DAG.getConstant(index, MVT::i32)),
4903 DAG.getConstant(index, MVT::i32));
4919 Ops.push_back(DAG.getConstant(I, MVT::i32));
4928 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4930 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4983 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5103 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5223 if (VT.getVectorElementType() == MVT::i32 ||
5237 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5243 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5270 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5296 DAG.getConstant(ExtractNum, MVT::i32));
5340 DAG.getConstant(Lane, MVT::i32));
5349 DAG.getConstant(Imm, MVT::i32));
5362 DAG.getConstant(Imm, MVT::i32));
5430 MVT::i32)));
5464 if (Op.getValueType() == MVT::i32 &&
5467 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5664 // Element types smaller than 32 bits are not legal, so use i32 elements.
5666 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5781 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5788 Y = DAG.getConstant(0xb000, MVT::i32);
5813 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5815 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5824 N1 = DAG.getConstant(0x89, MVT::i32);
5900 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5918 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5920 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5924 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5933 N1 = DAG.getConstant(2, MVT::i32);
5946 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6052 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6055 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6058 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6079 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6080 DAG.getConstant(15, MVT::i32),
6081 DAG.getConstant(0, MVT::i32),
6082 DAG.getConstant(9, MVT::i32),
6083 DAG.getConstant(13, MVT::i32),
6084 DAG.getConstant(0, MVT::i32)
6088 DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
6095 Cycles32 = DAG.getConstant(0, MVT::i32);
6101 Cycles32, DAG.getConstant(0, MVT::i32));
8278 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8279 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8328 AddcNode->getValueType(0) == MVT::i32 &&
8329 "Expect ADDC with two result values. First: i32");
8415 DAG.getVTList(MVT::i32, MVT::i32),
8554 if (VT != MVT::i32)
8579 MVT::i32)));
8586 MVT::i32)),
8599 MVT::i32)));
8607 MVT::i32)));
8609 DAG.getConstant(0, MVT::i32),Res);
8617 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8766 if (VT != MVT::i32)
8793 DAG.getConstant(Val, MVT::i32),
8794 DAG.getConstant(Mask, MVT::i32));
8819 DAG.getConstant(amt, MVT::i32));
8821 DAG.getConstant(Mask, MVT::i32));
8835 DAG.getConstant(lsb, MVT::i32));
8837 DAG.getConstant(Mask2, MVT::i32));
8856 DAG.getConstant(~Mask, MVT::i32));
8915 // vmovrrd(load f64) -> (load i32), (load i32)
8927 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8932 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8933 DAG.getConstant(4, MVT::i32));
8934 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
9072 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9073 DAG.getConstant(4, MVT::i32));
9085 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9136 // them up into i32 values.
9187 // i32, turn the build_vector into a sequence of insert_vector_elt.
9196 // Assume only bit cast to i32 will go away.
9197 if (Elt->getOperand(0).getValueType() == MVT::i32)
9211 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9229 V->getOperand(0).getValueType() == MVT::i32)
9233 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9237 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
9251 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9427 Tys[n++] = MVT::i32;
9627 // These instructions only exist converting from f32 to i32. We can handle
9638 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9639 DAG.getConstant(Log2_64(C), MVT::i32));
9678 // These instructions only exist converting from i32 to f32. We can handle
9695 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9696 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9878 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9896 DAG.getConstant(Cnt, MVT::i32));
9916 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9943 DAG.getConstant(Cnt, MVT::i32));
9952 DAG.getConstant(Cnt, MVT::i32));
9975 if (VT == MVT::i32 &&
10134 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10137 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10140 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10223 case MVT::i32: {
10277 // Lowering to i32/i16 if the size permits.
10279 return MVT::i32;
10338 case MVT::i32:
10363 case MVT::i32:
10403 case MVT::i32:
10431 case MVT::i32:
10488 case MVT::i32:
10565 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
11075 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;