Lines Matching refs:RetVT
139 unsigned FastEmitInst_extractsubreg(MVT RetVT,
218 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
520 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
523 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2097 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2107 if (RetVT != MVT::isVoid) {
2110 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2113 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2134 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2264 MVT RetVT;
2266 RetVT = MVT::isVoid;
2267 else if (!isTypeLegal(RetTy, RetVT))
2271 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2274 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2275 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2342 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2373 MVT RetVT;
2375 RetVT = MVT::isVoid;
2376 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2377 RetVT != MVT::i8 && RetVT != MVT::i1)
2381 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2382 RetVT != MVT::i16 && RetVT != MVT::i32) {
2385 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2386 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2493 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))